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change average and zcr frame to be 32 and 64 instead of 256 and 512
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@NouranAbdelaziz
NouranAbdelaziz committed Sep 12, 2024
1 parent 68ca364 commit 7215466
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Showing 6 changed files with 27 additions and 22 deletions.
8 changes: 4 additions & 4 deletions EF_I2S.yaml
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Expand Up @@ -7,8 +7,8 @@ info:
license: APACHE 2.0
author: Mohamed Shalan
email: [email protected]
version: v1.1.11
date: 10-09-2024
version: v1.1.12
date: 12-09-2024
category: digital
tags:
- peripheral
Expand Down Expand Up @@ -111,7 +111,7 @@ ports:
- name: avg_sel
width: 1
direction: input
description: 0 - 256 Samples, 1 - 512 Samples
description: 0 - 32 Samples, 1 - 64 Samples
- name: zcr_threshold
width: 32
direction: input
Expand All @@ -127,7 +127,7 @@ ports:
- name: zcr_sel
width: 1
direction: input
description: 0 - 256 Samples, 1 - 512 Samples
description: 0 - 32 Samples, 1 - 64 Samples
- name: vad_flag
width: 1
direction: output
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4 changes: 2 additions & 2 deletions README.md
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Expand Up @@ -207,11 +207,11 @@ The following are the bit definitions for the interrupt registers:
|avg_threshold|input|32|The samples average threshold|
|avg_flag|output|1|Flag raised when the samples average is above a threshold|
|avg_en|input|1|Enable average feature|
|avg_sel|input|1|0 - 256 Samples, 1 - 512 Samples|
|avg_sel|input|1|0 - 32 Samples, 1 - 64 Samples|
|zcr_threshold|input|32|The samples ZCR threshold|
|zcr_flag|output|1|Flag raised when the samples ZCR is above a threshold|
|zcr_en|input|1|Enable average feature|
|zcr_sel|input|1|0 - 256 Samples, 1 - 512 Samples|
|zcr_sel|input|1|0 - 32 Samples, 1 - 64 Samples|
|vad_flag|output|1|The VAD flag|
|channels|input|2|Channels used (left, right, or stereo)|
|en|input|1|Enable signal|
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14 changes: 7 additions & 7 deletions hdl/rtl/EF_I2S.pp.v
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Expand Up @@ -118,11 +118,11 @@ module EF_I2S #(parameter DW=32, AW=4) (
input wire [31:0] avg_threshold,
output wire avg_flag,
input wire avg_en,
input wire avg_sel, // 0: 256 samples, 1: 512 samples
input wire avg_sel, // 0: 32 samples, 1: 64 samples
input wire [31:0] zcr_threshold,
output wire zcr_flag,
input wire zcr_en,
input wire zcr_sel, // 0: 256 samples, 1: 512 samples
input wire zcr_sel, // 0: 32 samples, 1: 64 samples

output wire vad_flag,

Expand Down Expand Up @@ -185,7 +185,7 @@ module EF_I2S #(parameter DW=32, AW=4) (

// Averaging Logic
reg [31:0] sum;
reg [8:0] sum_ctr;
reg [5:0] sum_ctr;
wire [31:0] abs_sample_value = (fifo_wdata[31]) ? ~fifo_wdata : fifo_wdata;
always @ (posedge clk, negedge rst_n)
if(!rst_n)
Expand All @@ -194,7 +194,7 @@ module EF_I2S #(parameter DW=32, AW=4) (
if(sample_rdy & |(current_channel & channels))
sum_ctr <= sum_ctr + 1'b1;

wire sum_ctr_zero = avg_sel ? (sum_ctr == 9'b0) : (sum_ctr[7:0] == 8'b0);
wire sum_ctr_zero = avg_sel ? (sum_ctr == 6'b0) : (sum_ctr[4:0] == 5'b0);

always @ (posedge clk, negedge rst_n)
if(!rst_n)
Expand All @@ -205,13 +205,13 @@ module EF_I2S #(parameter DW=32, AW=4) (
else
if(avg_en) sum <= sum + abs_sample_value;

wire avg_gt_threshold = avg_sel ? (sum[31:9] > avg_threshold) : (sum[31:8] > avg_threshold);
wire avg_gt_threshold = avg_sel ? (sum[31:6] > avg_threshold) : (sum[31:5] > avg_threshold);
assign avg_flag = avg_en & (avg_gt_threshold);

// ZCR Logic
reg prev_sign;
reg [31:0] zcr;
reg [8:0] zc_ctr;
reg [5:0] zc_ctr;
always @ (posedge clk, negedge rst_n)
if(!rst_n)
zc_ctr <= 'b0;
Expand All @@ -225,7 +225,7 @@ module EF_I2S #(parameter DW=32, AW=4) (
else if(sample_rdy & |(current_channel & channels))
prev_sign <= fifo_wdata[31];

wire zc_ctr_zero = zcr_sel ? (zc_ctr == 9'b0) : (zc_ctr[7:0] == 8'b0);
wire zc_ctr_zero = zcr_sel ? (zc_ctr == 6'b0) : (zc_ctr[4:0] == 5'b0);

always @ (posedge clk, negedge rst_n)
if(!rst_n)
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14 changes: 7 additions & 7 deletions hdl/rtl/EF_I2S.v
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Original file line number Diff line number Diff line change
Expand Up @@ -118,11 +118,11 @@ module EF_I2S #(parameter DW=32, AW=4) (
input wire [31:0] avg_threshold,
output wire avg_flag,
input wire avg_en,
input wire avg_sel, // 0: 256 samples, 1: 512 samples
input wire avg_sel, // 0: 32 samples, 1: 64 samples
input wire [31:0] zcr_threshold,
output wire zcr_flag,
input wire zcr_en,
input wire zcr_sel, // 0: 256 samples, 1: 512 samples
input wire zcr_sel, // 0: 32 samples, 1: 64 samples

output wire vad_flag,

Expand Down Expand Up @@ -185,7 +185,7 @@ module EF_I2S #(parameter DW=32, AW=4) (

// Averaging Logic
reg [31:0] sum;
reg [8:0] sum_ctr;
reg [5:0] sum_ctr;
wire [31:0] abs_sample_value = (fifo_wdata[31]) ? ~fifo_wdata : fifo_wdata;
always @ (posedge clk, negedge rst_n)
if(!rst_n)
Expand All @@ -194,7 +194,7 @@ module EF_I2S #(parameter DW=32, AW=4) (
if(sample_rdy & |(current_channel & channels))
sum_ctr <= sum_ctr + 1'b1;

wire sum_ctr_zero = avg_sel ? (sum_ctr == 9'b0) : (sum_ctr[7:0] == 8'b0);
wire sum_ctr_zero = avg_sel ? (sum_ctr == 6'b0) : (sum_ctr[4:0] == 5'b0);

always @ (posedge clk, negedge rst_n)
if(!rst_n)
Expand All @@ -205,13 +205,13 @@ module EF_I2S #(parameter DW=32, AW=4) (
else
if(avg_en) sum <= sum + abs_sample_value;

wire avg_gt_threshold = avg_sel ? (sum[31:9] > avg_threshold) : (sum[31:8] > avg_threshold);
wire avg_gt_threshold = avg_sel ? (sum[31:6] > avg_threshold) : (sum[31:5] > avg_threshold);
assign avg_flag = avg_en & (avg_gt_threshold);

// ZCR Logic
reg prev_sign;
reg [31:0] zcr;
reg [8:0] zc_ctr;
reg [5:0] zc_ctr;
always @ (posedge clk, negedge rst_n)
if(!rst_n)
zc_ctr <= 'b0;
Expand All @@ -225,7 +225,7 @@ module EF_I2S #(parameter DW=32, AW=4) (
else if(sample_rdy & |(current_channel & channels))
prev_sign <= fifo_wdata[31];

wire zc_ctr_zero = zcr_sel ? (zc_ctr == 9'b0) : (zc_ctr[7:0] == 8'b0);
wire zc_ctr_zero = zcr_sel ? (zc_ctr == 6'b0) : (zc_ctr[4:0] == 5'b0);

always @ (posedge clk, negedge rst_n)
if(!rst_n)
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6 changes: 4 additions & 2 deletions verify/uvm-python/i2s_ref_model/i2s_ref_model.py
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Expand Up @@ -67,8 +67,10 @@ def write_bus(self, tr):
if tr.addr == self.regs.reg_name_to_address["CFG"]:
self.channels = self.regs.read_reg_value("CFG") & 0b11
self.left_justified = True if (self.regs.read_reg_value("CFG") >> 3) & 0b1 else False
self.avg_samples_size = 512 if self.regs.read_reg_value("CFG") & 0b1000000000 else 256
self.zcr_samples_size = 512 if self.regs.read_reg_value("CFG") & 0b10000000000 else 256
self.avg_samples_size = 512 if (self.regs.read_reg_value("CFG") & 0b10000000000) else 256
self.zcr_samples_size = 512 if (self.regs.read_reg_value("CFG") & 0b100000000000) else 256
uvm_info(self.tag, f"average samples number = {self.avg_samples_size} zcr samples number = {self.zcr_samples_size}", UVM_LOW)

if tr.addr == self.regs.reg_name_to_address["icr"] and tr.data != 0:
self.icr_changed.set()
if tr.addr == self.regs.reg_name_to_address["RX_FIFO_FLUSH"] and tr.data != 0:
Expand Down
3 changes: 3 additions & 0 deletions verify/uvm-python/test_lib.py
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Original file line number Diff line number Diff line change
Expand Up @@ -443,6 +443,9 @@ async def main_phase(self, phase):
sample = random.randint(0x0, 0xFFFFFFFF)
samples_list.append(sample)

# samples_list = [65440, 65441, 65437, 65436, 65441, 65440, 65438, 65438, 65439, 65442, 65442, 65444, 65442, 65446, 65447, 65445, 65448, 65450, 65451, 65449, 65446, 65437, 65436, 65433, 65430, 65432, 65434, 65433, 65430, 65434, 65443, 65444, 65446, 65447, 65446, 65438, 65436, 65435, 65435, 65434, 65432, 65432, 65432, 65429, 65424, 65429, 65426, 65432, 65436, 65434, 65432, 65429, 65429, 65431, 65437, 65444, 65449, 65443, 65434, 65432, 65433, 65434, 65440, 65440, 65440, 65442, 65446, 65444, 65444, 65447, 65449, 65448, 65450, 65447, 65445, 65445, 65449, 65454, 65457, 65459, 65457, 65450, 65452, 65453, 65455, 65454, 65453, 65453, 65459, 65463, 65465, 65460, 65459, 65458, 65453, 65457, 65459, 65463, 65464, 65456, 65453, 65459, 65460, 65463, 65462, 65459, 65461, 65467, 65467, 65474, 65472, 65471, 65471, 65473, 65477, 65479, 65479, 65473, 65467, 65465, 65464, 65464, 65459, 65461, 65460, 65460, 65464, 65463, 65465, 65468, 65466, 65464, 65466, 65472, 65472, 65469, 65467, 65471, 65468, 65464, 65466, 65461, 65458, 65459, 65456, 65455, 65454, 65457, 65458, 65457, 65459, 65447, 65443, 65447, 65455, 65455, 65457, 65456, 65453, 65452, 65449, 65455, 65457, 65457, 65452, 65447, 65448, 65443, 65446, 65448, 65449, 65448, 65446, 65445, 65443, 65448, 65449, 65442, 65444, 65448, 65451, 65444, 65445, 65445, 65445, 65447, 65449, 65447, 65447, 65448, 65443, 65443, 65446, 65446, 65446, 65447, 65446, 65442, 65438, 65440, 65441, 65441, 65446, 65448, 65446, 65447, 65446, 65447, 65447, 65443, 65442, 65443, 65446, 65444, 65441, 65443, 65449, 65445, 65443, 65441, 65442, 65441, 65439, 65441, 65444, 65447, 65444, 65441, 65441, 65442, 65440, 65443, 65454, 65453, 65453, 65453, 65458, 65462, 65457, 65453, 65453, 65451, 65452, 65457, 65462, 65463, 65459, 65446, 65444, 65452, 65453, 65455, 65453, 65453, 65454, 65456, 65463, 65471, 65472, 65469, 65464, 65461, 65461, 65462, 65463, 65461, 65468, 65471, 65471, 65468, 65468, 65468, 65470, 65469, 65468, 65467, 65462, 65464, 65471, 65473, 65478, 65481, 65473, 65465, 65463, 65471, 65481, 65486, 65485, 65474, 65475, 65473, 65478, 65484, 65485, 65482, 65477, 65479, 65476, 65478, 65475, 65475, 65476, 65484, 65493, 65488, 65485, 65478, 65474, 65481, 65489, 65490, 65492, 65493, 65488, 65482, 65480, 65485, 65488, 65481, 65478, 65479, 65488, 65488, 65486, 65487, 65489, 65491, 65493, 65498, 65498, 65500, 65497, 65497, 65499, 65500, 65499, 65498, 65495, 65491, 65490, 65492, 65490, 65487, 65487, 65491, 65494, 65495, 65490, 65484, 65479, 65479, 65480, 65483, 65489, 65490, 65489, 65489, 65489, 65489, 65483, 65486, 65488, 65489, 65491, 65493, 65495, 65492, 65488, 65485, 65485, 65494, 65496, 65495, 65496, 65494, 65499, 65494, 65487, 65485, 65485, 65485, 65485, 65480, 65476, 65476, 65479, 65483, 65486, 65483, 65481, 65481, 65482, 65482, 65479, 65478, 65484, 65487, 65482, 65483, 65485, 65485, 65485, 65480, 65480, 65476, 65471, 65467, 65468, 65471, 65472, 65467, 65466, 65468, 65471, 65472, 65474, 65470, 65469, 65463, 65465, 65470, 65480, 65479, 65477, 65475, 65466, 65464, 65465, 65467, 65469, 65470, 65470, 65466, 65462, 65466, 65470, 65472, 65476, 65477, 65474, 65473, 65476, 65475, 65479, 65477, 65474, 65477, 65478, 65479, 65477, 65469, 65472, 65478, 65478, 65482, 65481, 65476, 65473, 65476, 65482, 65488, 65493, 65489, 65482, 65478, 65483, 65489, 65485, 65483, 65480, 65475, 65472, 65473, 65476, 65480, 65484, 65487, 65490, 65488, 65490, 65490, 65491, 65494, 65498, 65497, 65493, 65488, 65484, 65480, 65486, 65491, 65486, 65483, 65493, 65491, 65486, 65481, 65479, 65479, 65478, 65485, 65492, 65495, 65495, 65494, 65490, 65490, 65492, 65488, 65487]
# for i in range (len(samples_list)):
# samples_list[i] = samples_list[i] << 16
samples_expected_average = self.get_expected_avg_threshold(samples_list, 16)


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