regenerate wrapper, documentation, and fw after zcr and avg features

EF_I2S.yaml

@@ -7,8 +7,8 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.1.10
-  date: 09-07-2024
+  version: v1.1.11
+  date: 10-09-2024
   category: digital
   tags:
     - peripheral

README.md

@@ -1,6 +1,5 @@
 # EF_I2S
 
-
 Two-wire I2S synchronous serial interface, compatible with I2S specification.
 - Receiver only
 - 32x32 Receive FIFO
@@ -17,7 +16,7 @@ Two-wire I2S synchronous serial interface, compatible with I2S specification.
 
 
 
-APB, AHBL, and Wishbone wrappers, generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility, are provided. All wrappers provide the same programmer's interface as outlined in the following sections.
+ APB, AHBL, and Wishbone wrappers, generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility, are provided. All wrappers provide the same programmer's interface as outlined in the following sections.
 
 
 ### Wrapped IP System Integration
@@ -57,8 +56,9 @@ The following table is the result for implementing the EF_I2S IP with different
 |RXDATA|0000|0x00000000|r|The received sample|
 |PR|0004|0x00000000|w|The Prescaler register; used to determine the sck signal frequency . $Prescaler = clk_freq/(2 x sck_freq) - 1$.|
 |AVGT|0008|0x00000000|w|The Average threshold|
-|CTRL|000c|0x00000000|w|Control Register; 0:Enable, 1:FIFO Enable.|
-|CFG|0010|0x00000201|w|Configuration Register, 0-1: Channels to read, '01': right, '10': left, '11': Both (stereo) 2: Sign Extend 3: Left Justify 4-8: Sample Size (0-31)|
+|ZCRT|000c|0x00000000|w|The ZCR threshold|
+|CTRL|0010|0x00000000|w|Control Register; 0:Enable, 1:FIFO Enable.|
+|CFG|0014|0x00000201|w|Configuration Register, 0-1: Channels to read, '01': right, '10': left, '11': Both (stereo) 2: Sign Extend 3: Left Justify 4-8: Sample Size (0-31)|
 |RX_FIFO_LEVEL|fe00|0x00000000|r|RX_FIFO Level Register|
 |RX_FIFO_THRESHOLD|fe04|0x00000000|w|RX_FIFO Level Threshold Register|
 |RX_FIFO_FLUSH|fe08|0x00000000|w|RX_FIFO Flush Register|
@@ -85,29 +85,38 @@ The Average threshold
 <img src="https://svg.wavedrom.com/{reg:[{name:'AVGT', bits:32},{bits: 0}], config: {lanes: 2, hflip: true}} "/>
 
 
-### CTRL Register [Offset: 0xc, mode: w]
+### ZCRT Register [Offset: 0xc, mode: w]
+
+The ZCR threshold
+<img src="https://svg.wavedrom.com/{reg:[{name:'ZCRT', bits:32},{bits: 0}], config: {lanes: 2, hflip: true}} "/>
+
+
+### CTRL Register [Offset: 0x10, mode: w]
 
 Control Register; 0:Enable, 1:FIFO Enable.
-<img src="https://svg.wavedrom.com/{reg:[{name:'en', bits:1},{name:'fifo_en', bits:1},{name:'avg_en', bits:1},{bits: 29}], config: {lanes: 2, hflip: true}} "/>
+<img src="https://svg.wavedrom.com/{reg:[{name:'en', bits:1},{name:'fifo_en', bits:1},{name:'avg_en', bits:1},{name:'zcr_en', bits:1},{bits: 28}], config: {lanes: 2, hflip: true}} "/>
 
 |bit|field name|width|description|
 |---|---|---|---|
 |0|en|1|Enable|
 |1|fifo_en|1|Fifo Enable|
 |2|avg_en|1|Averaging enable|
+|3|zcr_en|1|ZCR enable|
 
 
-### CFG Register [Offset: 0x10, mode: w]
+### CFG Register [Offset: 0x14, mode: w]
 
 Configuration Register, 0-1: Channels to read, '01': right, '10': left, '11': Both (stereo) 2: Sign Extend 3: Left Justify 4-8: Sample Size (0-31)
-<img src="https://svg.wavedrom.com/{reg:[{name:'channels', bits:2},{name:'sign_extend', bits:1},{name:'left_justified', bits:1},{name:'sample_size', bits:6},{bits: 22}], config: {lanes: 2, hflip: true}} "/>
+<img src="https://svg.wavedrom.com/{reg:[{name:'channels', bits:2},{name:'sign_extend', bits:1},{name:'left_justified', bits:1},{name:'sample_size', bits:6},{name:'AVGSEL', bits:1},{name:'ZCRSEL', bits:1},{bits: 20}], config: {lanes: 2, hflip: true}} "/>
 
 |bit|field name|width|description|
 |---|---|---|---|
 |0|channels|2|Channels to read, '01': right, '10': left, '11': Both (stereo)|
 |2|sign_extend|1|Sign Extend|
 |3|left_justified|1|Left justified flag|
 |4|sample_size|6|Sample size|
+|10|AVGSEL|1|Select the number of samples to average|
+|11|ZCRSEL|1|Select the number of samples to calculate the ZCR|
 
 
 ### RX_FIFO_LEVEL Register [Offset: 0xfe00, mode: r]
@@ -142,53 +151,40 @@ RX_FIFO Flush Register
 
 ### Interrupt Flags
 
-
-The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility.
-
+The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility. 
 
 Each register has a group of bits for the interrupt sources/flags.
 - `IM`: is used to enable/disable interrupt sources.
 
-
 - `RIS`: has the current interrupt status (interrupt flags) whether they are enabled or disabled.
 
-
 - `MIS`: is the result of masking (ANDing) RIS by IM.
 
-
 - `IC`: is used to clear an interrupt flag.
 
 
-
-
 The following are the bit definitions for the interrupt registers:
 
-
 |Bit|Flag|Width|Description|
 |---|---|---|---|
 |0|FIFOE|1|Receive FIFO is Empty|
 |1|FIFOA|1|FIFO level is above the set level threshold|
 |2|FIFOF|1|Receive FIFO is Full.|
 |3|AVGF|1|The avg is above the threshold.|
+|4|ZCRF|1|The ZCR is above the threshold.|
+|5|VADF|1|The Voice Activity Detector flag; active when both ZCR & AVG flags are active.|
 
+### The Interface 
 
-### The Interface
-
-
-<img src="docs/EF_I2S.svg" width="600"/>
-
-
-#### Module Parameters
 
+#### Module Parameters 
 
 |Parameter|Description|Default Value|
 |---|---|---|
 |DW|FIFO data width|32|
 |AW|FIFO Address width; Depth=2^AW|4|
 
-
-#### Ports
-
+#### Ports 
 
 |Port|Direction|Width|Description|
 |---|---|---|---|
@@ -211,6 +207,12 @@ The following are the bit definitions for the interrupt registers:
 |avg_threshold|input|32|The samples average threshold|
 |avg_flag|output|1|Flag raised when the samples average is above a threshold|
 |avg_en|input|1|Enable average feature|
+|avg_sel|input|1|0 - 256 Samples, 1 - 512 Samples|
+|zcr_threshold|input|32|The samples ZCR threshold|
+|zcr_flag|output|1|Flag raised when the samples ZCR is above a threshold|
+|zcr_en|input|1|Enable average feature|
+|zcr_sel|input|1|0 - 256 Samples, 1 - 512 Samples|
+|vad_flag|output|1|The VAD flag|
 |channels|input|2|Channels used (left, right, or stereo)|
 |en|input|1|Enable signal|
 
@@ -231,36 +233,36 @@ The following are the bit definitions for the interrupt registers:
 You can either clone repo or use [IPM](https://github.com/efabless/IPM) which is an open-source IPs Package Manager
 * To clone repo:
 ```git clone https://github.com/efabless/EF_I2S```
-* To download via IPM , follow installation guides [here](https://github.com/efabless/IPM/blob/main/README.md) then run
+* To download via IPM , follow installation guides [here](https://github.com/efabless/IPM/blob/main/README.md) then run 
 ```ipm install EF_I2S```
 ### Run cocotb UVM Testbench:
 In IP directory run:
-```shell
-cd verify/uvm-python/
-```
-##### To run testbench for design with APB
-To run all tests:
-```shell
-make run_all_tests BUS_TYPE=APB
-```
-To run a certain test:
-```shell
-make run_<test_name> BUS_TYPE=APB
-```
-To run all tests with a tag:
-```shell
-make run_all_tests TAG=<new_tag> BUS_TYPE=APB
-```
-##### To run testbench for design with APB
-To run all tests:
-```shell
-make run_all_tests BUS_TYPE=AHB
-```
-To run a certain test:
-```shell
-make run_<test_name> BUS_TYPE=AHB
+ ```shell
+ cd verify/uvm-python/
+ ```
+ ##### To run testbench for design with APB 
+ To run all tests:
+ ```shell
+ make run_all_tests BUS_TYPE=APB
+ ```
+ To run a certain test:
+ ```shell
+ make run_<test_name> BUS_TYPE=APB
+ ```
+ To run all tests with a tag: 
+ ```shell
+ make run_all_tests TAG=<new_tag> BUS_TYPE=APB
+ ```
+ ##### To run testbench for design with APB
+ To run all tests:
+ ```shell
+ make run_all_tests BUS_TYPE=AHB
+ ```
+ To run a certain test:
+ ```shell
+ make run_<test_name> BUS_TYPE=AHB
+ ```
+ To run all tests with a tag: 
+ ```shell
+ make run_all_tests TAG=<new_tag> BUS_TYPE=AHB
 ```
-To run all tests with a tag:
-```shell
-make run_all_tests TAG=<new_tag> BUS_TYPE=AHB
-```

fw/EF_I2S.c

@@ -43,13 +43,27 @@ void EF_I2S_enableAVG(uint32_t i2s_base){
     i2s->CTRL = control;
 }
 
+void EF_I2S_enableZCR(uint32_t i2s_base){
+    EF_I2S_TYPE* i2s = (EF_I2S_TYPE*)i2s_base;
+    int control = i2s->CTRL;
+    control |= EF_I2S_CTRL_REG_ZCR_EN_MASK;
+    i2s->CTRL = control;
+}
+
 void EF_I2S_disableAVG(uint32_t i2s_base){
     EF_I2S_TYPE* i2s = (EF_I2S_TYPE*)i2s_base;
     int control = i2s->CTRL;
     control &= ~EF_I2S_CTRL_REG_AVG_EN_MASK;
     i2s->CTRL = control;
 }
 
+void EF_I2S_disableZCR(uint32_t i2s_base){
+    EF_I2S_TYPE* i2s = (EF_I2S_TYPE*)i2s_base;
+    int control = i2s->CTRL;
+    control &= ~EF_I2S_CTRL_REG_ZCR_EN_MASK;
+    i2s->CTRL = control;
+}
+
 
 
 void EF_I2S_setConfigReg (uint32_t i2s_base, int config){
@@ -89,6 +103,12 @@ void EF_I2S_setAVGT(uint32_t i2s_base, int average){
     i2s->AVGT = average;
 }
 
+void EF_I2S_setZCRT(uint32_t i2s_base, int average){
+    EF_I2S_TYPE* i2s = (EF_I2S_TYPE*)i2s_base;
+
+    i2s->ZCRT = average;
+}
+
 
 
 int EF_I2S_getRxFifoLevel(uint32_t i2s_base){

fw/EF_I2S.h

@@ -18,6 +18,10 @@ void EF_I2S_enableAVG (uint32_t i2s_base);
 
 void EF_I2S_disableAVG (uint32_t i2s_base);
 
+void EF_I2S_enableZCR(uint32_t i2s_base);
+
+void EF_I2S_disableZCR(uint32_t i2s_base);
+
 void EF_I2S_setConfigReg (uint32_t i2s_base, int config);
 
 int EF_I2S_getConfigReg (uint32_t i2s_base);
@@ -28,6 +32,8 @@ int EF_I2S_getPrescaler(uint32_t i2s_base);
 
 void EF_I2S_setAVGT(uint32_t i2s_base, int average);
 
+void EF_I2S_setZCRT(uint32_t i2s_base, int average);
+
 int EF_I2S_getRxFifoLevel(uint32_t i2s_base);
 
 void EF_I2S_setRxFifoThreshold(uint32_t i2s_base, int threshold);

fw/EF_I2S_regs.h

@@ -33,6 +33,8 @@
 #define EF_I2S_CTRL_REG_FIFO_EN_MASK	0x2
 #define EF_I2S_CTRL_REG_AVG_EN_BIT	2
 #define EF_I2S_CTRL_REG_AVG_EN_MASK	0x4
+#define EF_I2S_CTRL_REG_ZCR_EN_BIT	3
+#define EF_I2S_CTRL_REG_ZCR_EN_MASK	0x8
 #define EF_I2S_CFG_REG_CHANNELS_BIT	0
 #define EF_I2S_CFG_REG_CHANNELS_MASK	0x3
 #define EF_I2S_CFG_REG_SIGN_EXTEND_BIT	2
@@ -41,6 +43,10 @@
 #define EF_I2S_CFG_REG_LEFT_JUSTIFIED_MASK	0x8
 #define EF_I2S_CFG_REG_SAMPLE_SIZE_BIT	4
 #define EF_I2S_CFG_REG_SAMPLE_SIZE_MASK	0x3f0
+#define EF_I2S_CFG_REG_AVGSEL_BIT	10
+#define EF_I2S_CFG_REG_AVGSEL_MASK	0x400
+#define EF_I2S_CFG_REG_ZCRSEL_BIT	11
+#define EF_I2S_CFG_REG_ZCRSEL_MASK	0x800
 #define EF_I2S_RX_FIFO_LEVEL_REG_LEVEL_BIT	0
 #define EF_I2S_RX_FIFO_LEVEL_REG_LEVEL_MASK	0xf
 #define EF_I2S_RX_FIFO_THRESHOLD_REG_THRESHOLD_BIT	0
@@ -52,14 +58,17 @@
 #define EF_I2S_FIFOA_FLAG	0x2
 #define EF_I2S_FIFOF_FLAG	0x4
 #define EF_I2S_AVGF_FLAG	0x8
+#define EF_I2S_ZCRF_FLAG	0x10
+#define EF_I2S_VADF_FLAG	0x20
 
 typedef struct _EF_I2S_TYPE_ {
 	__R 	RXDATA;
 	__W 	PR;
 	__W 	AVGT;
+	__W 	ZCRT;
 	__W 	CTRL;
 	__W 	CFG;
-	__R 	reserved_0[16251];
+	__R 	reserved_0[16250];
 	__R 	RX_FIFO_LEVEL;
 	__W 	RX_FIFO_THRESHOLD;
 	__W 	RX_FIFO_FLUSH;