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  1. minsoc minsoc Public

    minsoc from http://opencores.org/ocsvn/minsoc/minsoc

    Verilog 2

  2. source source Public

    Forked from lede-project/source

    Mirror of https://git.lede-project.org/?p=source.git Please send your PRs against this tree. They will be merged via staging trees and appear in this tree once the staging trees get merged back int…

    C 1

  3. ethmac ethmac Public

    ethmac from http://opencores.org/ocsvn/ethmac/ethmac

    Verilog 1

  4. uart16550 uart16550 Public

    uart16550 from http://opencores.org/ocsvn/uart16550/uart16550

    Verilog 1

  5. tinnnysu.github.io tinnnysu.github.io Public

    HTML

  6. blog blog Public

    HTML