James E. Stine, Jr. [email protected] Oklahoma State University School of Electrical and Computer Engineering VLSI Computer Architecture Research Group
Respository for ECEN 3233 Digital Logic Design at Oklahoma State University for the Fall 2022 semester!
Due Dates:
Although tentative due dates are given, pay attention to dates given on Canvas as well as in class. Later labs may be updated as we move throughout the semester, so make sure you pull often.
Location and Training:
Laboratory is held in ENDV 350 (https://ceat.okstate.edu/labs/endeavor/)
First week of class is important for logistics as well as getting access to Endeavor
Labs:
This repository is broken down into each laboratory and should be
cloned on your desktop. It contains System Verilog, testbenches,
documents relevant to each laboratyr, and a template to start working
on your Digital System Development Board (DSDB) by National
Instruments. More information about the board can be found here:
https://www.ni.com/docs/en-US/bundle/digital-systems-development-specs/resource/376641b.pdf
and in this repository.
The DSDB device was designed by AMD/Xilinx, but manufactured by a company called Digilent. There is some other information availble at Digilent's here.
