more ops, basic trace tests passing

nathanleiby · Dec 6, 2024 · 53d1965 · 53d1965
1 parent 710623d
commit 53d1965
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Showing 2 changed files with 43 additions and 25 deletions.
diff --git a/src/core.rs b/src/core.rs
@@ -51,8 +51,8 @@ pub enum AddressingMode {
 pub enum Flag {
     Negative,
     Overflow,
-    Break2,
-    Break,
+    // Break2,
+    // Break,
     Decimal,
     Interrupt,
     Zero,
@@ -100,11 +100,11 @@ impl Cpu {
         let rom = Rom::new_test_rom(vec![]);
         Cpu {
             pc: 0,
-            sp: 0xfd, // TODO: should it be inited to FD? or should something be put on it immediately?
+            sp: 0xfd,
             a: 0,
             x: 0,
             y: 0,
-            status: 0,
+            status: 0b100100,
             bus: Bus::new(rom),
         }
     }
@@ -215,8 +215,9 @@ impl Cpu {
         self.a = 0;
         self.x = 0;
         self.y = 0;
-        self.sp = 0xff;
+        self.sp = 0xfd;
         self.pc = self.mem_read_u16(0xFFFC);
+        // self.status = 0b100100; // TODO: This breaks my unit tests, but seems correct
         self.status = 0; // TODO: is this the correct initial state? I see various tests where both break flags are on
     }
 
@@ -243,20 +244,31 @@ impl Cpu {
                     OpName::STX => self.stx(&mode),
                     OpName::STY => self.sty(&mode),
                     OpName::BIT => self.bit(&mode),
+
                     OpName::NOP => self.nop(),
                     OpName::TXS => self.txs(),
                     OpName::TSX => self.tsx(),
                     OpName::PHA => self.pha(),
                     OpName::PLA => self.pla(),
                     OpName::PHP => self.php(),
                     OpName::PLP => self.plp(),
+
                     OpName::ORA => self.ora(&mode),
                     OpName::AND => self.and(&mode),
                     OpName::ADC => self.adc(&mode),
                     OpName::EOR => self.eor(&mode),
                     OpName::CMP => self.cmp(&mode),
                     OpName::CPX => self.cpx(&mode),
                     OpName::CPY => self.cpy(&mode),
+
+                    OpName::TAX => self.tax(),
+                    OpName::TXA => self.txa(),
+                    OpName::DEX => self.dex(),
+                    OpName::INX => self.inx(),
+                    OpName::TAY => self.tay(),
+                    OpName::TYA => self.tya(),
+                    OpName::DEY => self.dey(),
+                    OpName::INY => self.iny(),
                 }
                 self.pc += size - 1;
 
@@ -384,16 +396,6 @@ impl Cpu {
                 // RTS
                 0x60 => self.rts(),
 
-                // Register Instructions
-                0xAA => self.tax(),
-                0x8A => self.txa(),
-                0xCA => self.dex(),
-                0xE8 => self.inx(),
-                0xA8 => self.tay(),
-                0x98 => self.tya(),
-                0x88 => self.dey(),
-                0xC8 => self.iny(),
-
                 // SBC
                 0xE9 => {
                     self.sbc(&AddressingMode::Immediate);
@@ -887,8 +889,8 @@ impl Cpu {
             Flag::Zero => 1,
             Flag::Interrupt => 2,
             Flag::Decimal => 3,
-            Flag::Break => 4,
-            Flag::Break2 => 5,
+            // Flag::Break => 4,
+            // Flag::Break2 => 5,
             Flag::Overflow => 6,
             Flag::Negative => 7,
         };
@@ -909,8 +911,8 @@ impl Cpu {
             Flag::Zero => 1,
             Flag::Interrupt => 2,
             Flag::Decimal => 3,
-            Flag::Break => 4,
-            Flag::Break2 => 5,
+            // Flag::Break => 4,
+            // Flag::Break2 => 5,
             Flag::Overflow => 6,
             Flag::Negative => 7,
         };
@@ -1611,8 +1613,8 @@ mod tests {
         bus.mem_write(101, 0x33);
 
         //data
-        bus.mem_write(0x33, 00);
-        bus.mem_write(0x34, 04);
+        bus.mem_write(0x33, 0);
+        bus.mem_write(0x34, 4);
 
         //target cell
         bus.mem_write(0x400, 0xAA);

diff --git a/src/ops.rs b/src/ops.rs
@@ -2,7 +2,7 @@ use core::fmt;
 
 use crate::core::AddressingMode;
 
-// TODO: Stringify these
+#[allow(clippy::upper_case_acronyms)]
 #[derive(Debug, PartialEq, Eq)]
 pub enum OpName {
     LDA,
@@ -32,14 +32,20 @@ pub enum OpName {
     CMP,
     CPX,
     CPY,
+    TAX,
+    TXA,
+    DEX,
+    INX,
+    TAY,
+    TYA,
+    DEY,
+    INY,
     // SetFlag(Flag, bool),
 }
 
 impl fmt::Display for OpName {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match self {
-            _ => write!(f, "{:?}", self),
-        }
+        write!(f, "{:?}", self)
     }
 }
 
@@ -162,6 +168,16 @@ pub fn lookup_opcode(code: u8) -> Option<Op> {
         0x01 => (OpName::ORA, 2, AddressingMode::IndirectX),
         0x11 => (OpName::ORA, 2, AddressingMode::IndirectY),
 
+        // Register Instructions
+        0xAA => (OpName::TAX, 1, AddressingMode::None),
+        0x8A => (OpName::TXA, 1, AddressingMode::None),
+        0xCA => (OpName::DEX, 1, AddressingMode::None),
+        0xE8 => (OpName::INX, 1, AddressingMode::None),
+        0xA8 => (OpName::TAY, 1, AddressingMode::None),
+        0x98 => (OpName::TYA, 1, AddressingMode::None),
+        0x88 => (OpName::DEY, 1, AddressingMode::None),
+        0xC8 => (OpName::INY, 1, AddressingMode::None),
+
         _ => (OpName::TODO, 0, AddressingMode::None),
     };