unmapped cells in synthesis

[M0stafaRady]

got error from yosys when generating the gl of UART with wrapper
files in synthesis:

• <EF_UART>/hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
• <EF_UART>/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
• <EF_UART>/hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
• <IP_Utilities>/rtl/aucohl_lib.v
• <IP_Utilities>/rtl/aucohl_rtl.vh
• <EF_UART>//hdl/rtl/EF_UART.v

Errors from the log:

57. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

[shalan]

@M0stafaRady Are you sure that the netlist contains $ cells ?

I synthesized the RTL and the netlist is good to me. Here is the output from yosys stat command:

Number of cells: 2115
sky130_fd_sc_hd__a2111oi_0 3
sky130_fd_sc_hd__a211o_1 1
sky130_fd_sc_hd__a211oi_1 5
sky130_fd_sc_hd__a21boi_0 7
sky130_fd_sc_hd__a21o_1 1
sky130_fd_sc_hd__a21oi_1 84
sky130_fd_sc_hd__a221o_1 3
sky130_fd_sc_hd__a221oi_1 2
sky130_fd_sc_hd__a222oi_1 2
sky130_fd_sc_hd__a22o_1 8
sky130_fd_sc_hd__a22oi_1 5
sky130_fd_sc_hd__a2bb2oi_1 1
sky130_fd_sc_hd__a31o_1 1
sky130_fd_sc_hd__a31oi_1 8
sky130_fd_sc_hd__a32o_1 5
sky130_fd_sc_hd__a32oi_1 1
sky130_fd_sc_hd__a41oi_1 3
sky130_fd_sc_hd__and2_0 21
sky130_fd_sc_hd__and3_1 11
sky130_fd_sc_hd__and3b_1 1
sky130_fd_sc_hd__and4_1 2
sky130_fd_sc_hd__clkinv_1 124
sky130_fd_sc_hd__dfrtp_1 194
sky130_fd_sc_hd__dfstp_2 24
sky130_fd_sc_hd__dfxtp_1 291
sky130_fd_sc_hd__lpflow_inputiso1p_1 17
sky130_fd_sc_hd__lpflow_isobufsrc_1 25
sky130_fd_sc_hd__maj3_1 5
sky130_fd_sc_hd__mux2_1 367
sky130_fd_sc_hd__mux2i_1 23
sky130_fd_sc_hd__mux4_2 20
sky130_fd_sc_hd__nand2_1 134
sky130_fd_sc_hd__nand2b_1 8
sky130_fd_sc_hd__nand3_1 37
sky130_fd_sc_hd__nand3b_1 1
sky130_fd_sc_hd__nand4_1 22
sky130_fd_sc_hd__nand4b_1 1
sky130_fd_sc_hd__nor2_1 151
sky130_fd_sc_hd__nor2b_1 1
sky130_fd_sc_hd__nor3_1 39
sky130_fd_sc_hd__nor3b_1 5
sky130_fd_sc_hd__nor4_1 25
sky130_fd_sc_hd__nor4b_1 7
sky130_fd_sc_hd__nor4bb_1 1
sky130_fd_sc_hd__o2111a_1 1
sky130_fd_sc_hd__o2111ai_1 4
sky130_fd_sc_hd__o211a_1 1
sky130_fd_sc_hd__o211ai_1 6
sky130_fd_sc_hd__o21a_1 2
sky130_fd_sc_hd__o21ai_0 109
sky130_fd_sc_hd__o21bai_1 28
sky130_fd_sc_hd__o221a_1 1
sky130_fd_sc_hd__o221ai_1 2
sky130_fd_sc_hd__o22a_1 4
sky130_fd_sc_hd__o22ai_1 136
sky130_fd_sc_hd__o2bb2ai_1 2
sky130_fd_sc_hd__o31a_1 1
sky130_fd_sc_hd__o31ai_1 12
sky130_fd_sc_hd__o41ai_1 6
sky130_fd_sc_hd__or3_1 9
sky130_fd_sc_hd__or3b_1 4
sky130_fd_sc_hd__or4_1 5
sky130_fd_sc_hd__or4b_1 1
sky130_fd_sc_hd__xnor2_1 44
sky130_fd_sc_hd__xnor3_1 1
sky130_fd_sc_hd__xor2_1 39

It is clear that there is nothing unmapped!