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regenerate the wrappers with the new updates of the buswrap script
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@M0stafaRady
M0stafaRady committed Oct 7, 2024
1 parent d18c9cc commit b2af4de
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Showing 8 changed files with 295 additions and 107 deletions.
85 changes: 70 additions & 15 deletions hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,10 @@ module EF_I2S_AHBL #(
DW = 32,
AW = 4
) (




input wire HCLK,
input wire HRESETn,
input wire HWRITE,
Expand All @@ -124,16 +128,31 @@ module EF_I2S_AHBL #(
localparam RXDATA_REG_OFFSET = 16'h0000;
localparam PR_REG_OFFSET = 16'h0004;
localparam AVGT_REG_OFFSET = 16'h0008;
localparam CTRL_REG_OFFSET = 16'h000C;
localparam CFG_REG_OFFSET = 16'h0010;
localparam ZCRT_REG_OFFSET = 16'h000C;
localparam CTRL_REG_OFFSET = 16'h0010;
localparam CFG_REG_OFFSET = 16'h0014;
localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
localparam IM_REG_OFFSET = 16'hFF00;
localparam MIS_REG_OFFSET = 16'hFF04;
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;
wire clk = HCLK;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(HCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = HRESETn;


Expand Down Expand Up @@ -171,6 +190,12 @@ module EF_I2S_AHBL #(
wire [32-1:0] avg_threshold;
wire [1-1:0] avg_flag;
wire [1-1:0] avg_en;
wire [1-1:0] avg_sel;
wire [32-1:0] zcr_threshold;
wire [1-1:0] zcr_flag;
wire [1-1:0] zcr_en;
wire [1-1:0] zcr_sel;
wire [1-1:0] vad_flag;
wire [2-1:0] channels;
wire [1-1:0] en;

Expand All @@ -189,22 +214,31 @@ module EF_I2S_AHBL #(
else if(ahbl_we & (last_HADDR[16-1:0]==AVGT_REG_OFFSET))
AVGT_REG <= HWDATA[32-1:0];

reg [2:0] CTRL_REG;
reg [31:0] ZCRT_REG;
assign zcr_threshold = ZCRT_REG;
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) ZCRT_REG <= 0;
else if(ahbl_we & (last_HADDR[16-1:0]==ZCRT_REG_OFFSET))
ZCRT_REG <= HWDATA[32-1:0];

reg [3:0] CTRL_REG;
assign en = CTRL_REG[0 : 0];
assign fifo_en = CTRL_REG[1 : 1];
assign avg_en = CTRL_REG[2 : 2];
assign zcr_en = CTRL_REG[3 : 3];
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CTRL_REG <= 'h0;
else if(ahbl_we & (last_HADDR[16-1:0]==CTRL_REG_OFFSET))
CTRL_REG <= HWDATA[3-1:0];
CTRL_REG <= HWDATA[4-1:0];

reg [9:0] CFG_REG;
reg [11:0] CFG_REG;
assign channels = CFG_REG[1 : 0];
assign sign_extend = CFG_REG[2 : 2];
assign left_justified = CFG_REG[3 : 3];
assign sample_size = CFG_REG[9 : 4];
assign avg_sel = CFG_REG[10 : 10];
assign zcr_sel = CFG_REG[11 : 11];
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CFG_REG <= 'h201;
else if(ahbl_we & (last_HADDR[16-1:0]==CFG_REG_OFFSET))
CFG_REG <= HWDATA[10-1:0];
CFG_REG <= HWDATA[12-1:0];

wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
Expand All @@ -223,23 +257,30 @@ module EF_I2S_AHBL #(
else
RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;

reg [3:0] IM_REG;
reg [3:0] IC_REG;
reg [3:0] RIS_REG;
localparam GCLK_REG_OFFSET = 16'hFF10;
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0;
else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET))
GCLK_REG <= HWDATA[1-1:0];

wire[4-1:0] MIS_REG = RIS_REG & IM_REG;
reg [5:0] IM_REG;
reg [5:0] IC_REG;
reg [5:0] RIS_REG;

wire[6-1:0] MIS_REG = RIS_REG & IM_REG;
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IM_REG <= 0;
else if(ahbl_we & (last_HADDR[16-1:0]==IM_REG_OFFSET))
IM_REG <= HWDATA[4-1:0];
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IC_REG <= 4'b0;
IM_REG <= HWDATA[6-1:0];
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IC_REG <= 6'b0;
else if(ahbl_we & (last_HADDR[16-1:0]==IC_REG_OFFSET))
IC_REG <= HWDATA[4-1:0];
else IC_REG <= 4'd0;
IC_REG <= HWDATA[6-1:0];
else IC_REG <= 6'd0;

wire [0:0] FIFOE = fifo_empty;
wire [0:0] FIFOA = fifo_level_above;
wire [0:0] FIFOF = fifo_full;
wire [0:0] AVGF = avg_flag;
wire [0:0] ZCRF = zcr_flag;
wire [0:0] VADF = vad_flag;


integer _i_;
Expand All @@ -256,6 +297,12 @@ module EF_I2S_AHBL #(
for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
end
for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
end
for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
end
end

assign IRQ = |MIS_REG;
Expand Down Expand Up @@ -293,6 +340,12 @@ module EF_I2S_AHBL #(
.avg_threshold(avg_threshold),
.avg_flag(avg_flag),
.avg_en(avg_en),
.avg_sel(avg_sel),
.zcr_threshold(zcr_threshold),
.zcr_flag(zcr_flag),
.zcr_en(zcr_en),
.zcr_sel(zcr_sel),
.vad_flag(vad_flag),
.channels(channels),
.en(en),
.ws(ws),
Expand All @@ -304,6 +357,7 @@ module EF_I2S_AHBL #(
(last_HADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
(last_HADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :
(last_HADDR[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
(last_HADDR[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
(last_HADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
(last_HADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
(last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
Expand All @@ -313,6 +367,7 @@ module EF_I2S_AHBL #(
(last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
(last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
(last_HADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG :
(last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;

assign HREADYOUT = 1'b1;
Expand Down
77 changes: 64 additions & 13 deletions hdl/rtl/bus_wrappers/EF_I2S_AHBL.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,10 @@ module EF_I2S_AHBL #(
DW = 32,
AW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif
`AHBL_SLAVE_PORTS,
output wire [1-1:0] ws,
output wire [1-1:0] sck,
Expand All @@ -40,16 +44,31 @@ module EF_I2S_AHBL #(
localparam RXDATA_REG_OFFSET = `AHBL_AW'h0000;
localparam PR_REG_OFFSET = `AHBL_AW'h0004;
localparam AVGT_REG_OFFSET = `AHBL_AW'h0008;
localparam CTRL_REG_OFFSET = `AHBL_AW'h000C;
localparam CFG_REG_OFFSET = `AHBL_AW'h0010;
localparam ZCRT_REG_OFFSET = `AHBL_AW'h000C;
localparam CTRL_REG_OFFSET = `AHBL_AW'h0010;
localparam CFG_REG_OFFSET = `AHBL_AW'h0014;
localparam RX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE00;
localparam RX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE04;
localparam RX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE08;
localparam IM_REG_OFFSET = `AHBL_AW'hFF00;
localparam MIS_REG_OFFSET = `AHBL_AW'hFF04;
localparam RIS_REG_OFFSET = `AHBL_AW'hFF08;
localparam IC_REG_OFFSET = `AHBL_AW'hFF0C;
wire clk = HCLK;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk(HCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = HRESETn;


Expand All @@ -71,6 +90,12 @@ module EF_I2S_AHBL #(
wire [32-1:0] avg_threshold;
wire [1-1:0] avg_flag;
wire [1-1:0] avg_en;
wire [1-1:0] avg_sel;
wire [32-1:0] zcr_threshold;
wire [1-1:0] zcr_flag;
wire [1-1:0] zcr_en;
wire [1-1:0] zcr_sel;
wire [1-1:0] vad_flag;
wire [2-1:0] channels;
wire [1-1:0] en;

Expand All @@ -85,18 +110,25 @@ module EF_I2S_AHBL #(
assign avg_threshold = AVGT_REG;
`AHBL_REG(AVGT_REG, 0, 32)

reg [2:0] CTRL_REG;
reg [31:0] ZCRT_REG;
assign zcr_threshold = ZCRT_REG;
`AHBL_REG(ZCRT_REG, 0, 32)

reg [3:0] CTRL_REG;
assign en = CTRL_REG[0 : 0];
assign fifo_en = CTRL_REG[1 : 1];
assign avg_en = CTRL_REG[2 : 2];
`AHBL_REG(CTRL_REG, 'h0, 3)
assign zcr_en = CTRL_REG[3 : 3];
`AHBL_REG(CTRL_REG, 'h0, 4)

reg [9:0] CFG_REG;
reg [11:0] CFG_REG;
assign channels = CFG_REG[1 : 0];
assign sign_extend = CFG_REG[2 : 2];
assign left_justified = CFG_REG[3 : 3];
assign sample_size = CFG_REG[9 : 4];
`AHBL_REG(CFG_REG, 'h201, 10)
assign avg_sel = CFG_REG[10 : 10];
assign zcr_sel = CFG_REG[11 : 11];
`AHBL_REG(CFG_REG, 'h201, 12)

wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
Expand All @@ -109,18 +141,23 @@ module EF_I2S_AHBL #(
assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
`AHBL_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)

reg [3:0] IM_REG;
reg [3:0] IC_REG;
reg [3:0] RIS_REG;
localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10;
`AHBL_REG(GCLK_REG, 0, 1)

reg [5:0] IM_REG;
reg [5:0] IC_REG;
reg [5:0] RIS_REG;

`AHBL_MIS_REG(4)
`AHBL_REG(IM_REG, 0, 4)
`AHBL_IC_REG(4)
`AHBL_MIS_REG(6)
`AHBL_REG(IM_REG, 0, 6)
`AHBL_IC_REG(6)

wire [0:0] FIFOE = fifo_empty;
wire [0:0] FIFOA = fifo_level_above;
wire [0:0] FIFOF = fifo_full;
wire [0:0] AVGF = avg_flag;
wire [0:0] ZCRF = zcr_flag;
wire [0:0] VADF = vad_flag;


integer _i_;
Expand All @@ -137,6 +174,12 @@ module EF_I2S_AHBL #(
for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
end
for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
end
for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
end
end

assign IRQ = |MIS_REG;
Expand Down Expand Up @@ -174,6 +217,12 @@ module EF_I2S_AHBL #(
.avg_threshold(avg_threshold),
.avg_flag(avg_flag),
.avg_en(avg_en),
.avg_sel(avg_sel),
.zcr_threshold(zcr_threshold),
.zcr_flag(zcr_flag),
.zcr_en(zcr_en),
.zcr_sel(zcr_sel),
.vad_flag(vad_flag),
.channels(channels),
.en(en),
.ws(ws),
Expand All @@ -185,6 +234,7 @@ module EF_I2S_AHBL #(
(last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
(last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
(last_HADDR[`AHBL_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
(last_HADDR[`AHBL_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
(last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
(last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
(last_HADDR[`AHBL_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
Expand All @@ -194,6 +244,7 @@ module EF_I2S_AHBL #(
(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
(last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;

assign HREADYOUT = 1'b1;
Expand Down
43 changes: 18 additions & 25 deletions hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -102,10 +102,10 @@ module EF_I2S_APB #(
DW = 32,
AW = 4
) (
`ifdef USE_POWER_PINS
input VPWR,
input VGND,
`endif




input wire PCLK,
input wire PRESETn,
input wire PWRITE,
Expand Down Expand Up @@ -136,27 +136,20 @@ module EF_I2S_APB #(
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];

`ifdef FPGA
wire clk = PCLK;
`else
(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
`endif
.GCLK(clk_g),
.GATE(clk_gated_en),
.CLK(PCLK)
);

wire clk = clk_g;
`endif
reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(PCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = PRESETn;


Expand Down
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