Typecheck more things

ailment/__init__.py

@@ -3,16 +3,19 @@
 import logging
 
 from .block import Block
-from . import statement as Stmt
-from . import expression as Expr
-from .statement import Assignment
+from . import statement
+from . import expression
+from .statement import Assignment, Statement
 from .expression import Expression, Const, Tmp, Register, UnaryOp, BinaryOp
 from .converter_common import Converter
 from .manager import Manager
 from .block_walker import AILBlockWalker, AILBlockWalkerBase
 
 log = logging.getLogger(__name__)
 
+# REALLY BAD
+Expr = expression
+Stmt = statement
 
 available_converters: set[str] = set()
 
@@ -24,6 +27,7 @@
 except ImportError as e:
     log.debug("Could not import VEXIRSBConverter")
     log.debug(e)
+    VEXIRSBConverter = None
 
 try:
     from .converter_pcode import PCodeIRSBConverter
@@ -33,6 +37,7 @@
 except ImportError as e:
     log.debug("Could not import PCodeIRSBConverter")
     log.debug(e)
+    PCodeIRSBConverter = None
 
 
 class IRSBConverter(Converter):
@@ -57,8 +62,11 @@ def convert(irsb, manager):  # pylint:disable=arguments-differ
 __all__ = [
     "available_converters",
     "Block",
+    "expression",
+    "statement",
     "Stmt",
     "Expr",
+    "Statement",
     "Assignment",
     "Expression",
     "Const",
@@ -70,6 +78,6 @@ def convert(irsb, manager):  # pylint:disable=arguments-differ
     "IRSBConverter",
     "AILBlockWalkerBase",
     "AILBlockWalker",
-    *(["PCodeIRSBConverter"] if "pcode" in available_converters else []),
-    *(["VEXIRSBConverter"] if "vex" in available_converters else []),
+    "PCodeIRSBConverter",
+    "VEXIRSBConverter",
 ]

ailment/block.py

@@ -16,7 +16,7 @@ class Block:
         "idx",
     )
 
-    def __init__(self, addr, original_size, statements=None, idx=None):
+    def __init__(self, addr: int, original_size, statements=None, idx=None):
         self.addr = addr
         self.original_size = original_size
         self.statements: list["Statement"] = [] if statements is None else statements

ailment/block_walker.py

@@ -72,10 +72,10 @@ def walk_expression(
         self,
         expr: Expression,
         stmt_idx: int | None = None,
-        stmt: int | None = None,
+        stmt: Statement | None = None,
         block: Block | None = None,
     ):
-        return self._handle_expr(0, expr, stmt_idx, stmt, block)
+        return self._handle_expr(0, expr, stmt_idx or 0, stmt, block)
 
     def _handle_stmt(self, stmt_idx: int, stmt: Statement, block: Block | None) -> Any:
         try:

ailment/converter_vex.py

@@ -20,7 +20,6 @@
     ITE,
     Reinterpret,
     VEXCCallExpression,
-    TernaryOp,
 )
 from .converter_common import SkipConversionNotice, Converter
 
@@ -288,10 +287,68 @@ def Binop(expr, manager):
 
         bits = op._output_size_bits
 
-        extra_kwargs = {}
         if op_name == "DivMod":
-            extra_kwargs["from_bits"] = op._from_size if op._from_size is not None else operands[1].bits
-            extra_kwargs["to_bits"] = op._to_size if op._to_size is not None else operands[1].bits
+            op1_size = op._from_size if op._from_size is not None else operands[0].bits
+            op2_size = op._to_size if op._to_size is not None else operands[1].bits
+
+            if op2_size < op1_size:
+                # e.g., DivModU64to32
+                operands[1] = Convert(
+                    manager.next_atom(),
+                    op2_size,
+                    op1_size,
+                    op._from_signed != "U",
+                    operands[1],
+                    ins_addr=manager.ins_addr,
+                    vex_block_addr=manager.block_addr,
+                    vex_stmt_idx=manager.vex_stmt_idx,
+                )
+            chunk_bits = bits // 2
+
+            div = BinaryOp(
+                manager.next_atom(),
+                "Div",
+                operands,
+                signed,
+                ins_addr=manager.ins_addr,
+                vex_block_addr=manager.block_addr,
+                vex_stmt_idx=manager.vex_stmt_idx,
+                bits=op1_size,
+            )
+            truncated_div = Convert(
+                manager.next_atom(),
+                op1_size,
+                chunk_bits,
+                signed,
+                div,
+                ins_addr=manager.ins_addr,
+                vex_block_addr=manager.block_addr,
+                vex_stmt_idx=manager.vex_stmt_idx,
+            )
+            mod = BinaryOp(
+                manager.next_atom(),
+                "Mod",
+                operands,
+                signed,
+                ins_addr=manager.ins_addr,
+                vex_block_addr=manager.block_addr,
+                vex_stmt_idx=manager.vex_stmt_idx,
+                bits=op1_size,
+            )
+            truncated_mod = Convert(
+                manager.next_atom(),
+                op1_size,
+                chunk_bits,
+                signed,
+                mod,
+                ins_addr=manager.ins_addr,
+                vex_block_addr=manager.block_addr,
+                vex_stmt_idx=manager.vex_stmt_idx,
+            )
+
+            operands = [truncated_mod, truncated_div]
+            op_name = "Concat"
+            signed = False
 
         return BinaryOp(
             manager.next_atom(),
@@ -304,7 +361,6 @@ def Binop(expr, manager):
             bits=bits,
             vector_count=vector_count,
             vector_size=vector_size,
-            **extra_kwargs,
         )
 
     @staticmethod
@@ -332,14 +388,9 @@ def Triop(expr, manager):
                 bits=bits,
             )
 
-        return TernaryOp(
-            manager.next_atom(),
-            op_name,
-            operands,
-            ins_addr=manager.ins_addr,
-            vex_block_addr=manager.block_addr,
-            vex_stmt_idx=manager.vex_stmt_idx,
-            bits=bits,
+        raise TypeError(
+            "Please figure out what kind of operation this is (smart money says fused multiply) and convert it into "
+            "multiple binops"
         )
 
     @staticmethod