Unified Virtual Memory(UVM) support

[yechen3]

This work is adapted from UVM Smart for compatibility with GPGPU-Sim 4.0. The key features include:

1. A fully-associative last-level TLB and hence TLB lookup is performed in a single core cycle,
2. A multi-threaded page table (the last level shared) walker (configurable page table walk latency),
3. Workflow for replayable far-fault management (configurable far-fault handling latency),
4. PCIe transfer latency based on an equation derived from curve fitting transfer latency vs transfer size,
5. PCIe read and write stage queues and transactions (serialized transfers and queueing delay for transaction processing),
6. Prefetchers (Tree-based neighbourhood, Sequential-local 64KB, Random 4KB, On-demand migration),
7. Page replacement policies (Tree-based neighbourhood, Sequential-local 64KB, LRU 4KB, Random 4KB, LRU 2MB, LFU 2MB),
8. 32-bit access registers per 64KB (basic block),
9. Delayed migration based on an access-counter threshold,
10. Rounding up managed allocation and maintaining large page (2MB) level full-binary trees.
11. A runtime engine to detect underlying pattern in CPU-GPU interconnect traffic, a policy engine to choose and dynamically apply the best suitable memory management techniques.

However, it only works when L1 cache is disabled because of this line.