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Fix issues when trying to parameterize Verilog modules #945

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Fix issues when trying to parameterize Verilog modules #945

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Commits on Jul 12, 2023

  1. Try both lower-case transformed design unit name as well as original … 

    …format to fix issue with Verilog being case-sensitive.
    Piotr Rzeszut committed Jul 12, 2023
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Commits on Oct 5, 2023

  1. Move case-sensitivity check to get_test_bench (see VUnit#945)

    @piotrva
    piotrva committed Oct 5, 2023
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