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Fixed uarch table layout
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@JanLJL
JanLJL authored May 2, 2024
1 parent 2286da4 commit 5071d63
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76 changes: 38 additions & 38 deletions README.rst
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Expand Up @@ -142,57 +142,57 @@ Supported microarchitectures
-----------------------------
**x86 CPUs**

+----------+----------------+------------+
| Designer | Model/microarch| OSACA flag |
+==========+================+============+
| | | Sandy Bridge | ``SNB`` |
| | +----------------+------------+
| | | Ivy Bridge | ``IVB`` |
| | +----------------+------------+
| | | Haswell | ``HSW`` |
| | +----------------+------------+
| | | Broadwell | ``BDW`` |
| | +----------------+------------+
| | | Skylake-X | ``SKX`` |
| | Intel +----------------+------------+
| | | Cascadelake-X | ``CSX`` |
| | +----------------+------------+
| | | Icelake client | ``ICL`` |
| | +----------------+------------+
| | | Icelake server | ``ICX`` |
| | +----------------+------------+
| | | Sapphire Rapids| ``SPR`` |
+----------+----------------+------------+
| | | Naples / Zen 1 | ``ZEN1`` |
| | +----------------+------------+
| | AMD | Rome / Zen 2 | ``ZEN2`` |
| | +----------------+------------+
| | | Milan / Zen 3 | ``ZEN3`` |
+----------+----------------+------------+
+----------+-----------------+------------+
| Designer | Model/microarch | OSACA flag |
+==========+=================+============+
| Intel | Sandy Bridge | ``SNB`` |
+----------+-----------------+------------+
| Intel | Ivy Bridge | ``IVB`` |
+----------+-----------------+------------+
| Intel | Haswell | ``HSW`` |
+----------+-----------------+------------+
| Intel | Broadwell | ``BDW`` |
+----------+-----------------+------------+
| Intel | Skylake-X | ``SKX`` |
+----------+-----------------+------------+
| Intel | Cascadelake-X | ``CSX`` |
+----------+-----------------+------------+
| Intel | Icelake client | ``ICL`` |
+----------+-----------------+------------+
| Intel | Icelake server | ``ICX`` |
+----------+-----------------+------------+
| Intel | Sapphire Rapids | ``SPR`` |
+----------+-----------------+------------+
| AMD | Naples / Zen 1 | ``ZEN1`` |
+----------+-----------------+------------+
| AMD | Rome / Zen 2 | ``ZEN2`` |
+----------+-----------------+------------+
| AMD | Milan / Zen 3 | ``ZEN3`` |
+----------+-----------------+------------+

**ARM AArch64 CPUs**

+-----------+-------------------+-------------+
| Designer | Model/microarch | OSACA flag |
+===========+===================+=============+
| | | Cortex-A72 | ``A72`` |
| | +-------------------+-------------+
| | ARM | Neoverse N1 | ``N1`` |
| | +-------------------+-------------+
| | | Neoverse V2 | ``V2`` |
| ARM | Cortex-A72 | ``A72`` |
+-----------+-------------------+-------------+
| Marvell | ThunderX2 | ``TX2`` |
| ARM | Neoverse N1 | ``N1`` |
+-----------+-------------------+-------------+
| Fujitsu | FX700/A64FX | ``A64FX`` |
| ARM | Neoverse V2 | ``V2`` |
+-----------+-------------------+-------------+
| HiSilicon | TaiShan v110 | ``TSV110`` |
| Marvell | ThunderX2 | ``TX2`` |
+-----------+-------------------+-------------+
| Apple | M1-Firestorm | ``M1`` |
| Fujitsu | FX700/A64FX | ``A64FX`` |
+-----------+-------------------+-------------+
| NVIDIA | Neoverse V2/Grace | ``V2`` |
| HiSilicon | TaiShan v110 | ``TSV110`` |
+-----------+-------------------+-------------+
| Apple | M1-Firestorm | ``M1`` |
+-----------+-------------------+-------------+
| NVIDIA | Neoverse V2/Grace | ``V2`` |
+-----------+-------------------+-------------+

______________________
----

Hereinafter OSACA's scope of function will be described.

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