dynamic assignment

[SikoVerilog]

I have 2 register one I locking other but first one swwe property is Bool type but other property is FieldNode type I can't get the value kindly help me how can I get the value in dynamic assignment?? or share the function who can help me in python to get more details of that property.

[amykyta3]

Can you provide some more details? I don't quite understand what the question is. Perhaps a sample of SystemRDL code may help.

[SikoVerilog]

I wan help on
<FieldNode counter.cntrl.lock at 0x103c90be0>
this portion how I can get more details and better control in python

[amykyta3]

(edited your post to fix formatting)

Since the swwe property is assigned a reference to another field, it's value is represented by a FieldNode reference object.
Please see the node documentation for more details on what you can query about these objects: https://systemrdl-compiler.readthedocs.io/en/stable/api/node.html#fieldnode

[SikoVerilog]

I tried to find some function who share the details of the reference object but failed to find can you please the list of functions who can help in python.

[amykyta3]

Please see the link I shared as that documents how to query the details of the reference object.
For example:

value = fld.get_property("swwe")
if isinstance(value, FieldNode):
    print(value.get_path())
    print(value.inst_name)
    print(value.get_property("hw"))
    # ... etc

[SikoVerilog]

it only work for
count.value->swwe = cntrl.lock;

but in case of count.value->swwe = cntrl.lock->swwe
I got <PropRef_swwe counter.cntrl.lock->swwe at 0x105464cd0>

[SikoVerilog]

in case of count.value->swwe = cntrl.lock->swwe
this work
if isinstance(swwe, PropRef_swwe): print( type(swwe)) print(swwe.name) print(swwe.node.inst_name) print(swwe.node.get_property(swwe.name))

output
<class 'systemrdl.properties.prop_refs.PropRef_swwe'> swwe lock True

can you please confirm is its a write way??

[bbqbob]

It is interesting that the topic of locks came up as I was just trying create lock bits myself. Unlike other description languages like OpenTitan's, the notion of lock bits isn't a first class concept, or even an example as far as I've seen. I've created the following code myself, but as I am new at SystemRDL, I am not confident in these examples. It would be great if someone with more experience could comment as to whether this really accomplishes what I intended.

addrmap example {
    name = "Lock and Guard bits";
    desc = "registers:
             	1) one with lock-bit in the register
				2) lock, in another register, until reset
				3 )lock and unlock register controlling writes to another register";

	// example 1: lock bit in a register
	// this registers contains its own lock bit
	reg control_with_lockbit_t {
		name = "control_reg 1";
		desc = "lock bit in this register";
		
		// lock bit 
		//     resets to 0
		//     writing 1 sets the lock bit, writing 0 has no effect
		//     once set, lock bit cannot be cleared (other than by reset))
		//     when the lock bit is set, the other fields in this register can no longer be written
		field lock_bit_t {
			hw = r;
			sw = rw;
			woset;
		} lock = 1'b0;
		
		// cbit_1 can only be written white the lock bit is 0
		//      if the cbit_1 is written on the same transaction as lock_bit is 1,
		//         the written value is committed to cbit_1, and further alteration is not possible
		field ctl_bit {
			name = "control bit";
			// storage element that continually drives the wire
			hw = r;
			sw = rw;
			swwel;
		} cbit_1;
		cbit_1->swwel = lock;
	} reg_control_with_lock_bit;

	
	// example 2:
    //   control register can be written until lock, then it cannot be written
	//   only reset would unlock writes to the register

	reg lock_reg_t {
		name = "lock register";
		desc = "one (or more) lock bits for other registers";
		field ary_lock_bit_t {
			sw = rw;
			woset;
		};
		ary_lock_bit_t lock_1 = 1'b0;
	};
	
	// this registers is locked based on a bit in the lock register
	reg control_locked_by_other_t {
		name = "control register 2";
		desc = "one (or more) lock bits for other registers";
		// seems like a write enable should appply to whole reg, but this doesn't work
		//swwel;  
		field some_bit_t {
			sw = rw;
			swwel;
		};
		some_bit_t bit1;
		some_bit_t bit2;
		
	};
	
	// create a lock register, but no unlock register
	lock_reg_t reg_locks;
	// register that will be locked
	control_locked_by_other_t reg_control_with_lockreg;

	//the following do not work
	//reg_control_with_lockreg.some_bit->sw = reg_locks.lock_1->next ? r : rw;
	//reg_control_with_lockreg.some_bit->swwe = reg_locks.lock_1->next ? false : true;
	
	// combersome, but set the enable for each bit
	reg_control_with_lockreg.bit1->swwel = reg_locks.lock_1;
	reg_control_with_lockreg.bit2->swwel = reg_locks.lock_1;


	//example 3: lock and unlock (aka guard)
	//   control register can be written until lock, then it cannot be written
	//   an unlock register will re-enable writing to the register
	
	// this register allows unlocking for other registers
	reg unlock_reg_t {
		name = "unlock register";
		desc = "one (or more) unlock bits for other registers";
		field ary_unlock_bit_t {
			sw = rw;
			woclr;
		};
		ary_unlock_bit_t lock_1 = 1'b0;
	};
	
	// create a lock register and an unlock register
	lock_reg_t reg_guards;
	alias reg_guards unlock_reg_t reg_unguards;
	
	// register that will be guarded
	control_locked_by_other_t reg_control_with_guard;
	reg_control_with_guard.bit1->swwel = reg_guards.lock_1;
	reg_control_with_guard.bit2->swwel = reg_guards.lock_1;
};

[amykyta3]

Looks like you got the right idea!
Examples 1 & 2 are exactly what I would have recommended. If you want, you can omit the swwel; inside the field since you're assigning it a reference later anyways.

For example 3, I'd have to study it a bit more. I admit I have not done too much with aliases yet so I have not internalized the rules for those as much. I think it should work?
An alternative method that doesn't use aliases could be to use the singlepulse property to generate a strobe that clears the reg:

	reg unlock_reg_t {
		field ary_unlock_bit_t {
			sw = w;
			singlepulse;
		};
		ary_unlock_bit_t unlock = 1'b0;
	};
	
	// create a lock register and an unlock register
	lock_reg_t reg_guards;
	unlock_reg_t reg_unguards;
	
	// register that will be guarded
	control_locked_by_other_t reg_control_with_guard;
	reg_control_with_guard.bit1->swwel = reg_guards.lock_1;
	reg_control_with_guard.bit2->swwel = reg_guards.lock_1;

	// clear lock bit
	reg_guards.lock_1->hwclr = reg_unguards.unlock;