Notation for user defined property for fixed point and arbitrary length integers

[jeras]

I would like to define a user defined property for defining the next two bit vector types.

• arbitrary length integer,
• fixed point.
  The question is what notation to use, I will list a few options, the provided examples are for the same type.

The property would be used in VHDL/Verilog and software header code generators.

Wikipedia provides a few notations, one of them looks a good fit.
I used the Q notation before (ARM version):

SQ16.8
UQ168

VHDL provides a standardized syntax for fixed point values:

sfixed (16-1 downto -8)
ufixed (16-1 downto -8)

And for arbitrary length integers there is:

signed   (24-1 downto 0)
unsigned (24-1 downto 0)

Verilog/SystemVerilog does not provide a standardized syntax for fixed point values, but is is common to use this:

logic   signed [16-1:-8]
logic unsigned [16-1:-8]

Arbitrary length integers are defined with the common vector notation and the signed/unsigned specifier (added in Verilog 2001):

logic   signed [24-1:0]
logic unsigned [24-1:0]

Xilinx also provides type definitions for the C++ language based HLS:

ap_fixed<24, 16>
ap_ufixed<24, 16>

I did not go in deep enough to find out whether there is a clear distinction between fixed point and arbitrary length integer.

The default choice for SystemRDL would be the Verilog notation, since a lot of the syntax is already based on Verilog.
The problem I see is, Verilog lacks a clear distinction between fixed point and arbitrary length integer.
VHDL provides the strongest standardization and the cleares distinction between types.

One option for Verilog syntax would be to just provide the signed/unsigned specifier without a range for arbitrary length integer, withe the length of the vector extracted from the field width. And for fixed point use the full type with the range.