Repositories list

• gem5

  Public
  The official repository for the gem5 computer-system architecture simulator.

  C++

  •

  BSD 3-Clause "New" or "Revised" License

  •1.3k•0•0•0•Updated Feb 2, 2025Feb 2, 2025

• ADSProject

  Public
  This repository contains the basic files for the class project of the course "Architecture of Digital Systems I"

  processor-architecturechiselhardware-designs+ 2teaching-materialsrisc-v

  Scala

  •16•3•0•1•Updated Jan 21, 2025Jan 21, 2025

• SecureBOOM

  Public
  Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)

  securityhardwarespectre+ 4hardware-securitydesign-methodsmeltdownformal-verification-for-designers

  Verilog

  •

  Other

  •1•9•0•0•Updated Jan 17, 2025Jan 17, 2025

• UPEC

  Public
  Unique Program Execution Checking (UPEC)

  HTML

  •0•0•0•0•Updated Jan 13, 2025Jan 13, 2025

• thesis-template

  Public
  LaTeX template for Bachelor and Master theses at EIS chair

  TeX

  •0•0•0•0•Updated Dec 3, 2024Dec 3, 2024

• VDSProject

  Public
  This repository contains the basic files for the class project of the course "Verification of Digital Systems"

  C++

  •46•5•0•1•Updated Nov 21, 2024Nov 21, 2024

• IOPMP-TLUL

  Public
  SystemVerilog

  •1•0•0•0•Updated Nov 7, 2024Nov 7, 2024

• UPEC-DIT

  Public
  This repository contains experiments and results on using UPEC to prove data-independent timing in hardware.

  2•5•0•0•Updated Oct 10, 2024Oct 10, 2024

• Security-Conscious-Hardware

  Public
  Collection of experiments on data-oblivious hardware designs that dynamically adjust their latency

  SystemVerilog

  •1•1•0•0•Updated Jul 25, 2024Jul 25, 2024

• RISCV-Core

  Public
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany

  pipelineteachingcomputer-architecture+ 1risc-v

  C

  •9•11•0•0•Updated Jul 12, 2024Jul 12, 2024

• VeriCHERI

  Public
  SystemVerilog

  •0•2•0•0•Updated Jul 5, 2024Jul 5, 2024

• .github

  Public
  0•0•0•0•Updated Feb 22, 2024Feb 22, 2024

• rocket-chip-inclusive-cache

  Public
  An RTL generator for a last-level shared inclusive TileLink cache controller

  Scala

  •

  Apache License 2.0

  •20•0•0•0•Updated Nov 19, 2023Nov 19, 2023

• OpenTitan_with_Access_Control

  Public
  OpenTitan Silver Release v5 copy for security improvements

  SystemVerilog

  •

  Apache License 2.0

  •2•2•0•0•Updated Nov 9, 2023Nov 9, 2023

• fault-attack-monitors

  Public
  SystemVerilog

  •0•0•0•0•Updated May 24, 2023May 24, 2023

• upec-boom-verification-suite

  Public
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.

  Verilog

  •2•17•1•0•Updated Mar 2, 2023Mar 2, 2023

• Speckle

  Public
  A wrapper for the SPEC CPU2017 benchmark suite.

  Shell

  •53•0•0•0•Updated Dec 8, 2022Dec 8, 2022

• riscv-boom

  Public
  SonicBOOM: The Berkeley Out-of-Order Machine

  Scala

  •

  BSD 3-Clause "New" or "Revised" License

  •434•0•0•0•Updated May 10, 2022May 10, 2022

• BOOMv3-delay-on-miss-dcache

  Public
  The repository contains the source files for the BOOM v3, patched against transient execution attacks using UPEC iterative patch cycles.

  Scala

  •

  BSD 3-Clause "New" or "Revised" License

  •1•0•0•0•Updated Nov 16, 2021Nov 16, 2021

• symbolic-pmp

  Public
  This repository contains a symbolic and secure configuration template for the RISC-V Physical Memory Protection (PMP) to be used in SV/SVA based verification flows.

  SystemVerilog

  •0•3•0•0•Updated Apr 13, 2021Apr 13, 2021