[FIRRTL] FART: Does not process modules not reachable from the main module

[youngar]

Two identical modules, both annotated with FART:

FIRRTL version 4.0.0
circuit Foo: %[[
  {"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Foo>r"},
  {"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Bar>r"}
]]
  public module Foo:
    input c : Clock
    input i : UInt<8>
    input r : AsyncReset
    output o : UInt<8>
    reg reg : UInt<8>, c
    connect reg, i
    connect o, reg

  public module Bar:
    input c : Clock
    input i : UInt<8>
    input r : AsyncReset
    output o : UInt<8>
    reg reg : UInt<8>, c
    connect reg, i
    connect o, reg

gives:

  module Foo(
  input        c,
  input  [7:0] i,
  input        r,
  output [7:0] o
);

  reg [7:0] reg_0;
  always @(posedge c or posedge r) begin
    if (r)
      reg_0 <= 8'h0;
    else
      reg_0 <= i;
  end // always @(posedge, posedge)
  `ifdef ENABLE_INITIAL_REG_
    `ifdef FIRRTL_BEFORE_INITIAL
      `FIRRTL_BEFORE_INITIAL
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin
      automatic logic [31:0] _RANDOM[0:0];
      `ifdef INIT_RANDOM_PROLOG_
        `INIT_RANDOM_PROLOG_
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT
        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
        reg_0 = _RANDOM[/*Zero width*/ 1'b0][7:0];
      `endif // RANDOMIZE_REG_INIT
      if (r)
        reg_0 = 8'h0;
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL
      `FIRRTL_AFTER_INITIAL
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign o = reg_0;
endmodule

module Bar(
  input        c,
  input  [7:0] i,
  input        r,
  output [7:0] o
);

  reg [7:0] reg_0;
  always @(posedge c)
    reg_0 <= i;
  `ifdef ENABLE_INITIAL_REG_
    `ifdef FIRRTL_BEFORE_INITIAL
      `FIRRTL_BEFORE_INITIAL
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin
      automatic logic [31:0] _RANDOM[0:0];
      `ifdef INIT_RANDOM_PROLOG_
        `INIT_RANDOM_PROLOG_
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT
        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
        reg_0 = _RANDOM[/*Zero width*/ 1'b0][7:0];
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL
      `FIRRTL_AFTER_INITIAL
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign o = reg_0;
endmodule

The module Bar does not have an asynchronous reset, while I would expect the contents to be identical to Foo.

The issue is that it only visits modules recursively through instance operations, starting at the top level module:

circt/lib/Dialect/FIRRTL/Transforms/InferResets.cpp

Lines 1459 to 1467 in f75bbd7

	// Gather the domains.
	auto &instGraph = getAnalysis<InstanceGraph>();
	auto module = dyn_cast<FModuleOp>(*instGraph.getTopLevelNode()->getModule());
	if (!module) {
	LLVM_DEBUG(llvm::dbgs()
	<< "Skipping circuit because main module is no `firrtl.module`");
	return success();
	}
	buildDomains(module, InstancePath{}, Value{}, instGraph);