diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
index e13d976..a89674f 100644
--- a/verify/uvm-python/Makefile
+++ b/verify/uvm-python/Makefile
@@ -4,7 +4,7 @@ MODULE   ?= top_module
 AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
 APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
 WB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
-HDL_FILES ?= $(PWD)/IP_Utilities/rtl/aucohl_lib.v $(PWD)/IP_Utilities/rtl/aucohl_rtl.vh  $(PWD)/../../hdl/rtl/EF_UART.v 
+HDL_FILES ?= $(PWD)/../../ip/IP_Utilities/rtl/aucohl_lib.v $(PWD)/../../ip/IP_Utilities/rtl/aucohl_rtl.vh  $(PWD)/../../hdl/rtl/EF_UART.v 
 VERILOG_SOURCES ?=  $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
 RTL_MACROS += ""
 BUS_TYPE ?= APB
@@ -29,6 +29,7 @@ GL_MACROS += -DGL -DFUNCTIONAL  $(RTL_MACROS) -DUNIT_DELAY=\#1
 PRE_SYS_FILES = $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
 PDK_DIR = $(HOME)/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/
 PDK_FILES = $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v # get this from openlane logs in the future 
+# IPM_DIR = $(HOME)/.ipm
 POST_SYS_FILES = $(PWD)/top.v $(VIP_FILES) $(PWD)/../../hdl/gl/synthesis/nl/$(DESIGN_NAME).nl.v
 
 # RTL_MACROS ?= "-DSKIP_WAVE_DUMP"
@@ -47,11 +48,6 @@ SIM_PATH := $(PWD)/sim/$(SIM_TAG)
 
 # Check and clone EF_UVM repository at the beginning of the Makefile execution
 
-clone_ip_util := $(shell if [ ! -d "IP_Utilities" ]; then \
-	echo "Cloning the IP_Utilities repository..."; \
-	git clone https://github.com/shalan/IP_Utilities.git; \
-fi;)
-
 clone_ef_uvm := $(shell if [ ! -d "EF_UVM" ]; then \
 	echo "Cloning the EF_UVM repository..."; \
 	git clone https://github.com/efabless/EF_UVM.git; \
diff --git a/verify/uvm-python/uart_seq_lib/uart_config.py b/verify/uvm-python/uart_seq_lib/uart_config.py
index 6d3d75e..1f12007 100644
--- a/verify/uvm-python/uart_seq_lib/uart_config.py
+++ b/verify/uvm-python/uart_seq_lib/uart_config.py
@@ -29,7 +29,8 @@ def __init__(
     async def body(self):
         await super().body()
         # get register names/address conversion dict
-
+        # enable clock gated 
+        await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1)
         # randomly config uart
         # first disabled the uart
         await self.send_req(