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bsg_cache_to_test_dram does not support multiple outstanding reads per channel #616

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dpetrisko opened this issue Dec 11, 2022 · 1 comment
Open

bsg_cache_to_test_dram does not support multiple outstanding reads per channel #616

dpetrisko opened this issue Dec 11, 2022 · 1 comment
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The DRAM data return is stored in a PISO and then drained. For some configurations if the core is slow and DRAM is fast, the data can back up in the PISO. If there are multiple outstanding reads, then the PISO can overflow.

Multiple outstanding requests can come from non-blocking caches or a prefetcher for a blocking cache.

The simplest fix is to have a DRAM response data fifo the size of a (parametrized) number of read requests, so that it degenerates to the current hardware for 1 outstanding read request
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@tommydcjung @mrutt92 thoughts?

@dpetrisko dpetrisko self-assigned this Dec 16, 2022
@dpetrisko dpetrisko added the bug Something isn't working label Dec 16, 2022
dpetrisko pushed a commit that referenced this issue Jan 26, 2023
@tommydcjung
Icache block size (#616)
9184f42 
* prevent unnecessary icache read after icache miss; get rid of mem_addr_sent, icache miss pc dff

* icache miss test

* fix

* fix

* icache miss flush test

* simplify

* clean

* clean

* icache two words block

* save

* save

* fix

* use sram no write mask

* fix energy benchmark

* update

* update path to vcache

* fix

* fix

* energy_loop_test

* energy_loop_test run parallel

* icache block size = 4

* synth fix

* add comments/link to diagram

* add icache_block_size_in_words_p at toplevel
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