From 42c2e00f7fd401966c02b447b2e0c1adb6421b37 Mon Sep 17 00:00:00 2001 From: ashutosh321607 Date: Thu, 28 Nov 2019 03:37:53 +0530 Subject: [PATCH] Processor Design Sources file and xdc with .bit file added --- end_game/end_game.cache/wt/gui_resources.wdf | 39 + .../wt/java_command_handlers.wdf | 21 + end_game/end_game.cache/wt/project.wpc | 4 + end_game/end_game.cache/wt/synthesis.wdf | 39 + .../end_game.cache/wt/synthesis_details.wdf | 3 + end_game/end_game.cache/wt/webtalk_pa.xml | 86 +++ end_game/end_game.cache/wt/xsim.wdf | 4 + end_game/end_game.hw/end_game.lpr | 8 + end_game/end_game.hw/hw_1/hw.xml | 16 + .../end_game.hw/webtalk/_xsim_webtallk.info | 5 + .../end_game.hw/webtalk/labtool_webtalk.log | 8 + .../webtalk/usage_statistics_ext_labtool.html | 45 ++ .../webtalk/usage_statistics_ext_labtool.xml | 39 + end_game/end_game.ip_user_files/README.txt | 1 + end_game/end_game.runs/.jobs/vrs_config_1.xml | 5 + end_game/end_game.runs/.jobs/vrs_config_2.xml | 8 + end_game/end_game.runs/.jobs/vrs_config_3.xml | 8 + end_game/end_game.runs/.jobs/vrs_config_4.xml | 8 + end_game/end_game.runs/.jobs/vrs_config_5.xml | 8 + end_game/end_game.runs/.jobs/vrs_config_6.xml | 8 + end_game/end_game.runs/.jobs/vrs_config_7.xml | 8 + end_game/end_game.runs/.jobs/vrs_config_8.xml | 8 + end_game/end_game.runs/fib.bit | Bin 0 -> 2192112 bytes end_game/end_game.runs/impl_1/ISEWrap.js | 244 ++++++ end_game/end_game.runs/impl_1/ISEWrap.sh | 63 ++ .../impl_1/_Vivado_Implementation.queue.rst | 0 .../impl_1/_init_design.begin.rst | 5 + .../end_game.runs/impl_1/_init_design.end.rst | 0 .../impl_1/_opt_design.begin.rst | 5 + .../end_game.runs/impl_1/_opt_design.end.rst | 0 .../impl_1/_place_design.begin.rst | 5 + .../impl_1/_place_design.end.rst | 0 .../impl_1/_route_design.begin.rst | 5 + .../impl_1/_route_design.end.rst | 0 .../end_game.runs/impl_1/_vivado.begin.rst | 5 + end_game/end_game.runs/impl_1/_vivado.end.rst | 0 .../impl_1/_write_bitstream.begin.rst | 5 + .../impl_1/_write_bitstream.end.rst | 0 end_game/end_game.runs/impl_1/gen_run.xml | 158 ++++ end_game/end_game.runs/impl_1/htr.txt | 9 + end_game/end_game.runs/impl_1/init_design.pb | Bin 0 -> 1583 bytes end_game/end_game.runs/impl_1/main.bit | Bin 0 -> 2192112 bytes end_game/end_game.runs/impl_1/main.tcl | 149 ++++ end_game/end_game.runs/impl_1/main.vdi | 406 ++++++++++ .../impl_1/main_clock_utilization_routed.rpt | 193 +++++ .../impl_1/main_control_sets_placed.rpt | 79 ++ .../end_game.runs/impl_1/main_drc_opted.rpt | 49 ++ .../end_game.runs/impl_1/main_drc_routed.pb | Bin 0 -> 37 bytes .../end_game.runs/impl_1/main_drc_routed.rpt | 49 ++ .../end_game.runs/impl_1/main_drc_routed.rpx | Bin 0 -> 1626 bytes .../end_game.runs/impl_1/main_io_placed.rpt | 280 +++++++ .../impl_1/main_methodology_drc_routed.rpt | 655 +++++++++++++++++ .../impl_1/main_methodology_drc_routed.rpx | Bin 0 -> 32733 bytes end_game/end_game.runs/impl_1/main_opt.dcp | Bin 0 -> 175625 bytes end_game/end_game.runs/impl_1/main_placed.dcp | Bin 0 -> 210047 bytes .../impl_1/main_power_routed.rpt | 148 ++++ .../impl_1/main_power_routed.rpx | Bin 0 -> 101030 bytes .../impl_1/main_power_summary_routed.pb | Bin 0 -> 722 bytes .../end_game.runs/impl_1/main_route_status.pb | Bin 0 -> 44 bytes .../impl_1/main_route_status.rpt | 11 + end_game/end_game.runs/impl_1/main_routed.dcp | Bin 0 -> 236756 bytes .../impl_1/main_timing_summary_routed.rpt | 175 +++++ .../impl_1/main_timing_summary_routed.rpx | Bin 0 -> 18531 bytes .../impl_1/main_utilization_placed.pb | Bin 0 -> 276 bytes .../impl_1/main_utilization_placed.rpt | 209 ++++++ end_game/end_game.runs/impl_1/opt_design.pb | Bin 0 -> 7079 bytes end_game/end_game.runs/impl_1/place_design.pb | Bin 0 -> 11605 bytes end_game/end_game.runs/impl_1/project.wdf | 31 + end_game/end_game.runs/impl_1/route_design.pb | Bin 0 -> 9872 bytes end_game/end_game.runs/impl_1/rundef.js | 40 + end_game/end_game.runs/impl_1/runme.bat | 10 + end_game/end_game.runs/impl_1/runme.log | 405 ++++++++++ end_game/end_game.runs/impl_1/runme.sh | 47 ++ .../impl_1/usage_statistics_webtalk.html | 694 ++++++++++++++++++ .../impl_1/usage_statistics_webtalk.xml | 623 ++++++++++++++++ end_game/end_game.runs/impl_1/vivado.jou | 12 + end_game/end_game.runs/impl_1/vivado.pb | Bin 0 -> 149 bytes .../end_game.runs/impl_1/write_bitstream.pb | Bin 0 -> 3414 bytes .../synth_1/.Xil/main_propImpl.xdc | 61 ++ end_game/end_game.runs/synth_1/ISEWrap.js | 244 ++++++ end_game/end_game.runs/synth_1/ISEWrap.sh | 63 ++ .../synth_1/_Vivado_Synthesis.queue.rst | 0 .../end_game.runs/synth_1/_vivado.begin.rst | 5 + .../end_game.runs/synth_1/_vivado.end.rst | 0 .../end_game.runs/synth_1/fsm_encoding.os | 5 + end_game/end_game.runs/synth_1/gen_run.xml | 98 +++ end_game/end_game.runs/synth_1/htr.txt | 9 + end_game/end_game.runs/synth_1/main.dcp | Bin 0 -> 71107 bytes end_game/end_game.runs/synth_1/main.tcl | 46 ++ end_game/end_game.runs/synth_1/main.vds | 640 ++++++++++++++++ .../synth_1/main_utilization_synth.pb | Bin 0 -> 276 bytes .../synth_1/main_utilization_synth.rpt | 182 +++++ end_game/end_game.runs/synth_1/rundef.js | 36 + end_game/end_game.runs/synth_1/runme.bat | 10 + end_game/end_game.runs/synth_1/runme.log | 639 ++++++++++++++++ end_game/end_game.runs/synth_1/runme.sh | 43 ++ end_game/end_game.runs/synth_1/vivado.jou | 12 + end_game/end_game.runs/synth_1/vivado.pb | Bin 0 -> 94913 bytes end_game/end_game.sim/sim_1/behav/compile.bat | 11 + end_game/end_game.sim/sim_1/behav/compile.log | 30 + .../end_game.sim/sim_1/behav/elaborate.bat | 9 + .../end_game.sim/sim_1/behav/elaborate.log | 35 + end_game/end_game.sim/sim_1/behav/glbl.v | 71 ++ .../end_game.sim/sim_1/behav/main_simu.tcl | 11 + .../sim_1/behav/main_simu_behav.wdb | Bin 0 -> 36357 bytes .../sim_1/behav/main_simu_vlog.prj | 17 + .../end_game.sim/sim_1/behav/simulate.bat | 9 + .../end_game.sim/sim_1/behav/simulate.log | 2 + end_game/end_game.sim/sim_1/behav/webtalk.jou | 12 + end_game/end_game.sim/sim_1/behav/webtalk.log | 13 + .../sim_1/behav/webtalk_9084.backup.jou | 12 + .../sim_1/behav/webtalk_9084.backup.log | 13 + end_game/end_game.sim/sim_1/behav/xelab.pb | Bin 0 -> 6144 bytes .../main_simu_behav/Compile_Options.txt | 1 + .../main_simu_behav/TempBreakPointFile.txt | 1 + .../webtalk/_xsim_webtallk.info | 5 + .../webtalk/usage_statistics_ext_xsim.html | 53 ++ .../webtalk/usage_statistics_ext_xsim.xml | 44 ++ .../behav/xsim.dir/main_simu_behav/xsim.dbg | Bin 0 -> 21356 bytes .../behav/xsim.dir/main_simu_behav/xsim.mem | Bin 0 -> 5761 bytes .../behav/xsim.dir/main_simu_behav/xsim.reloc | Bin 0 -> 3679 bytes .../behav/xsim.dir/main_simu_behav/xsim.rtti | Bin 0 -> 251 bytes .../xsim.dir/main_simu_behav/xsim.svtype | Bin 0 -> 62 bytes .../behav/xsim.dir/main_simu_behav/xsim.type | Bin 0 -> 24 bytes .../behav/xsim.dir/main_simu_behav/xsim.xdbg | Bin 0 -> 5912 bytes .../xsim.dir/main_simu_behav/xsimSettings.ini | 26 + .../xsim.dir/main_simu_behav/xsimcrash.log | 65 ++ .../behav/xsim.dir/main_simu_behav/xsimk.exe | Bin 0 -> 102645 bytes .../xsim.dir/main_simu_behav/xsimkernel.log | 7 + .../behav/xsim.dir/xil_defaultlib/alu.sdb | Bin 0 -> 2129 bytes .../behav/xsim.dir/xil_defaultlib/clk@div.sdb | Bin 0 -> 1437 bytes .../behav/xsim.dir/xil_defaultlib/control.sdb | Bin 0 -> 9759 bytes .../behav/xsim.dir/xil_defaultlib/cpu.sdb | Bin 0 -> 2537 bytes .../behav/xsim.dir/xil_defaultlib/glbl.sdb | Bin 0 -> 3821 bytes .../behav/xsim.dir/xil_defaultlib/main.sdb | Bin 0 -> 2209 bytes .../xsim.dir/xil_defaultlib/main_simu.sdb | Bin 0 -> 2172 bytes .../behav/xsim.dir/xil_defaultlib/pc.sdb | Bin 0 -> 1243 bytes .../behav/xsim.dir/xil_defaultlib/regfile.sdb | Bin 0 -> 2113 bytes .../xsim.dir/xil_defaultlib/seven_seg.sdb | Bin 0 -> 3702 bytes .../behav/xsim.dir/xil_defaultlib/sram.sdb | Bin 0 -> 1673 bytes .../xil_defaultlib/xil_defaultlib.rlx | 15 + .../sim_1/behav/xsim.dir/xsim.svtype | Bin 0 -> 8 bytes end_game/end_game.sim/sim_1/behav/xsim.ini | 1 + end_game/end_game.sim/sim_1/behav/xvlog.log | 30 + end_game/end_game.sim/sim_1/behav/xvlog.pb | Bin 0 -> 5379 bytes .../constrs_1/new/my_constraint.xdc | 72 ++ end_game/end_game.srcs/sim_1/new/cpusim.v | 76 ++ end_game/end_game.srcs/sim_1/new/main_tb.v | 51 ++ end_game/end_game.srcs/sources_1/new/alu.v | 26 + .../end_game.srcs/sources_1/new/clock_div.v | 17 + .../end_game.srcs/sources_1/new/control.v | 213 ++++++ end_game/end_game.srcs/sources_1/new/cpu.v | 21 + end_game/end_game.srcs/sources_1/new/main.v | 46 ++ end_game/end_game.srcs/sources_1/new/pc.v | 16 + end_game/end_game.srcs/sources_1/new/reg.v | 30 + .../end_game.srcs/sources_1/new/seven_seg.v | 243 ++++++ end_game/end_game.srcs/sources_1/new/sram.v | 56 ++ end_game/end_game.xpr | 210 ++++++ 158 files changed, 8811 insertions(+) create mode 100644 end_game/end_game.cache/wt/gui_resources.wdf create mode 100644 end_game/end_game.cache/wt/java_command_handlers.wdf create mode 100644 end_game/end_game.cache/wt/project.wpc create mode 100644 end_game/end_game.cache/wt/synthesis.wdf create mode 100644 end_game/end_game.cache/wt/synthesis_details.wdf create mode 100644 end_game/end_game.cache/wt/webtalk_pa.xml create mode 100644 end_game/end_game.cache/wt/xsim.wdf create mode 100644 end_game/end_game.hw/end_game.lpr create mode 100644 end_game/end_game.hw/hw_1/hw.xml create mode 100644 end_game/end_game.hw/webtalk/_xsim_webtallk.info create mode 100644 end_game/end_game.hw/webtalk/labtool_webtalk.log create mode 100644 end_game/end_game.hw/webtalk/usage_statistics_ext_labtool.html create mode 100644 end_game/end_game.hw/webtalk/usage_statistics_ext_labtool.xml create mode 100644 end_game/end_game.ip_user_files/README.txt create mode 100644 end_game/end_game.runs/.jobs/vrs_config_1.xml create mode 100644 end_game/end_game.runs/.jobs/vrs_config_2.xml create mode 100644 end_game/end_game.runs/.jobs/vrs_config_3.xml create mode 100644 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+ + diff --git a/end_game/end_game.cache/wt/xsim.wdf b/end_game/end_game.cache/wt/xsim.wdf new file mode 100644 index 0000000..0f875db --- /dev/null +++ b/end_game/end_game.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/end_game/end_game.hw/end_game.lpr b/end_game/end_game.hw/end_game.lpr new file mode 100644 index 0000000..8cc4078 --- /dev/null +++ b/end_game/end_game.hw/end_game.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/end_game/end_game.hw/hw_1/hw.xml b/end_game/end_game.hw/hw_1/hw.xml new file mode 100644 index 0000000..e21c501 --- /dev/null +++ b/end_game/end_game.hw/hw_1/hw.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/end_game/end_game.hw/webtalk/_xsim_webtallk.info b/end_game/end_game.hw/webtalk/_xsim_webtallk.info new file mode 100644 index 0000000..9809513 --- /dev/null +++ b/end_game/end_game.hw/webtalk/_xsim_webtallk.info @@ -0,0 +1,5 @@ +1574444035 +0 +2 +0 +93a5a53b-c035-4f1c-b3f0-43883c241131 diff --git a/end_game/end_game.hw/webtalk/labtool_webtalk.log b/end_game/end_game.hw/webtalk/labtool_webtalk.log new file mode 100644 index 0000000..50fa955 --- /dev/null +++ b/end_game/end_game.hw/webtalk/labtool_webtalk.log @@ -0,0 +1,8 @@ + +****** Webtalk v2017.1 (64-bit) + **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017 + **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source C:/Users/hp/end_game/end_game.hw/webtalk/labtool_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Fri Nov 22 23:03:57 2019... diff --git a/end_game/end_game.hw/webtalk/usage_statistics_ext_labtool.html b/end_game/end_game.hw/webtalk/usage_statistics_ext_labtool.html new file mode 100644 index 0000000..4015139 --- /dev/null +++ b/end_game/end_game.hw/webtalk/usage_statistics_ext_labtool.html @@ -0,0 +1,45 @@ +Device Usage Statistics Report +

LABTOOL Usage Report


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software_version_and_target_device
betaFALSEbuild_version1846317
date_generatedFri Nov 22 23:03:55 2019os_platformWIN64
product_versionVivado v2017.1 (64-bit)project_id93a5a53b-c035-4f1c-b3f0-43883c241131
project_iteration1random_ida20516f5-6568-4922-95cb-fd63966b3ff7
registration_id211458424_1777531420_210673176_760route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-6700 CPU @ 3.40GHzcpu_speed3408 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram17.000 GBtotal_processors1

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vivado_usage

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labtool
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usage
cable=Digilent/Basys3/15000000:chain=0362D093pgmcnt=01:00:00
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+ diff --git a/end_game/end_game.ip_user_files/README.txt b/end_game/end_game.ip_user_files/README.txt new file mode 100644 index 0000000..9015e04 --- /dev/null +++ b/end_game/end_game.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. 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a/end_game/end_game.runs/impl_1/ISEWrap.js b/end_game/end_game.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..8284d2d --- /dev/null +++ b/end_game/end_game.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/end_game/end_game.runs/impl_1/ISEWrap.sh b/end_game/end_game.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/end_game/end_game.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/end_game/end_game.runs/impl_1/_Vivado_Implementation.queue.rst b/end_game/end_game.runs/impl_1/_Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/impl_1/_init_design.begin.rst b/end_game/end_game.runs/impl_1/_init_design.begin.rst new file mode 100644 index 0000000..acb8c6a --- /dev/null +++ b/end_game/end_game.runs/impl_1/_init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/end_game/end_game.runs/impl_1/_init_design.end.rst b/end_game/end_game.runs/impl_1/_init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/impl_1/_opt_design.begin.rst b/end_game/end_game.runs/impl_1/_opt_design.begin.rst new file mode 100644 index 0000000..acb8c6a --- /dev/null +++ b/end_game/end_game.runs/impl_1/_opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/end_game/end_game.runs/impl_1/_opt_design.end.rst b/end_game/end_game.runs/impl_1/_opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/impl_1/_place_design.begin.rst b/end_game/end_game.runs/impl_1/_place_design.begin.rst new file mode 100644 index 0000000..acb8c6a --- /dev/null +++ b/end_game/end_game.runs/impl_1/_place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/end_game/end_game.runs/impl_1/_place_design.end.rst b/end_game/end_game.runs/impl_1/_place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/impl_1/_route_design.begin.rst b/end_game/end_game.runs/impl_1/_route_design.begin.rst new file mode 100644 index 0000000..acb8c6a --- /dev/null +++ b/end_game/end_game.runs/impl_1/_route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/end_game/end_game.runs/impl_1/_route_design.end.rst b/end_game/end_game.runs/impl_1/_route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/impl_1/_vivado.begin.rst b/end_game/end_game.runs/impl_1/_vivado.begin.rst new file mode 100644 index 0000000..619a2ca --- /dev/null +++ b/end_game/end_game.runs/impl_1/_vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/end_game/end_game.runs/impl_1/_vivado.end.rst b/end_game/end_game.runs/impl_1/_vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/impl_1/_write_bitstream.begin.rst b/end_game/end_game.runs/impl_1/_write_bitstream.begin.rst new file mode 100644 index 0000000..acb8c6a --- /dev/null +++ b/end_game/end_game.runs/impl_1/_write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/end_game/end_game.runs/impl_1/_write_bitstream.end.rst b/end_game/end_game.runs/impl_1/_write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/impl_1/gen_run.xml b/end_game/end_game.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..d8ecf85 --- /dev/null +++ b/end_game/end_game.runs/impl_1/gen_run.xml @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/end_game/end_game.runs/impl_1/htr.txt b/end_game/end_game.runs/impl_1/htr.txt new file mode 100644 index 0000000..85f912a --- /dev/null +++ b/end_game/end_game.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. 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wNAr1mJkHx(VL4oCgrV^HfAZF!ZO&Vx&Na=raCYX?T$l_02K*b?3jYTFf5OS(HUIzs literal 0 HcmV?d00001 diff --git a/end_game/end_game.runs/impl_1/main.tcl b/end_game/end_game.runs/impl_1/main.tcl new file mode 100644 index 0000000..2891d9c --- /dev/null +++ b/end_game/end_game.runs/impl_1/main.tcl @@ -0,0 +1,149 @@ +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Common 17-41} -limit 10000000 + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a35tcpg236-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/hp/end_game/end_game.cache/wt [current_project] + set_property parent.project_path C:/Users/hp/end_game/end_game.xpr [current_project] + set_property ip_output_repo C:/Users/hp/end_game/end_game.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet C:/Users/hp/end_game/end_game.runs/synth_1/main.dcp + read_xdc C:/Users/hp/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc + link_design -top main -part xc7a35tcpg236-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force main_opt.dcp + catch { report_drc -file main_drc_opted.rpt } + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + implement_debug_core + place_design + write_checkpoint -force main_placed.dcp + catch { report_io -file main_io_placed.rpt } + catch { report_utilization -file main_utilization_placed.rpt -pb main_utilization_placed.pb } + catch { report_control_sets -verbose -file main_control_sets_placed.rpt } + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force main_routed.dcp + catch { report_drc -file main_drc_routed.rpt -pb main_drc_routed.pb -rpx main_drc_routed.rpx } + catch { report_methodology -file main_methodology_drc_routed.rpt -rpx main_methodology_drc_routed.rpx } + catch { report_power -file main_power_routed.rpt -pb main_power_summary_routed.pb -rpx main_power_routed.rpx } + catch { report_route_status -file main_route_status.rpt -pb main_route_status.pb } + catch { report_clock_utilization -file main_clock_utilization_routed.rpt } + catch { report_timing_summary -warn_on_violation -max_paths 10 -file main_timing_summary_routed.rpt -rpx main_timing_summary_routed.rpx } + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force main_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force main.mmi } + write_bitstream -force main.bit + catch {write_debug_probes -no_partial_ltxfile -quiet -force debug_nets} + catch {file copy -force debug_nets.ltx main.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/end_game/end_game.runs/impl_1/main.vdi b/end_game/end_game.runs/impl_1/main.vdi new file mode 100644 index 0000000..a8cb299 --- /dev/null +++ b/end_game/end_game.runs/impl_1/main.vdi @@ -0,0 +1,406 @@ +#----------------------------------------------------------- +# Vivado v2017.1 (64-bit) +# SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017 +# IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 +# Start of session at: Sat Nov 23 00:05:51 2019 +# Process ID: 4936 +# Current directory: C:/Users/hp/end_game/end_game.runs/impl_1 +# Command line: vivado.exe -log main.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source main.tcl -notrace +# Log file: C:/Users/hp/end_game/end_game.runs/impl_1/main.vdi +# Journal file: C:/Users/hp/end_game/end_game.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source main.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/hp/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc] +Finished Parsing XDC File [C:/Users/hp/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 588.727 ; gain = 286.953 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +INFO: [DRC 23-27] Running DRC with 2 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.440 . Memory (MB): peak = 599.543 ; gain = 10.816 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 1 inverter(s) to 8 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 199e44df7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 34 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1105a4869 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 7 cells and removed 14 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1931c868d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1931c868d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1931c868d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1931c868d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 132bfa9e8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1154.863 ; gain = 0.000 +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1154.863 ; gain = 566.137 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/hp/end_game/end_game.runs/impl_1/main_opt.dcp' has been generated. +Command: report_drc -file main_drc_opted.rpt +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/hp/end_game/end_game.runs/impl_1/main_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +INFO: [DRC 23-27] Running DRC with 2 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +INFO: [DRC 23-27] Running DRC with 2 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 121ed6241 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1643462e3 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.669 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 22f440c62 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.686 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 22f440c62 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.688 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 22f440c62 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.688 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1712aec50 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.870 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1712aec50 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.873 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 206c29ca8 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.881 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 28653ff41 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.888 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 28653ff41 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.889 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1d3680a9f + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d3680a9f + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Ending Placer Task | Checksum: 114cef4fc + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 +36 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/hp/end_game/end_game.runs/impl_1/main_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1154.863 ; gain = 0.000 +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1154.863 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +INFO: [DRC 23-27] Running DRC with 2 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: e7fcca7e ConstDB: 0 ShapeSum: 2cd22a7e RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 170549879 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1248.793 ; gain = 93.930 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 170549879 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1254.777 ; gain = 99.914 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 170549879 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1254.777 ; gain = 99.914 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 10d7fb730 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: e1814700 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 27 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 +Phase 4 Rip-up And Reroute | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 +Phase 6 Post Hold Fix | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0762975 % + Global Horizontal Routing Utilization = 0.107236 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions. +Phase 7 Route finalize | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.766 ; gain = 105.902 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: ca204202 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.766 ; gain = 105.902 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.766 ; gain = 105.902 + +Routing Is Done. +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.766 ; gain = 105.902 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1260.766 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/hp/end_game/end_game.runs/impl_1/main_routed.dcp' has been generated. +Command: report_drc -file main_drc_routed.rpt -pb main_drc_routed.pb -rpx main_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/hp/end_game/end_game.runs/impl_1/main_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file main_methodology_drc_routed.rpt -rpx main_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/hp/end_game/end_game.runs/impl_1/main_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file main_power_routed.rpt -pb main_power_summary_routed.pb -rpx main_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +51 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +Command: write_bitstream -force main.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +Running DRC as a precondition to command write_bitstream +Command: report_drc (run_mandatory_drcs) for: bitstream_checks +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./main.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). +61 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1702.137 ; gain = 405.188 +INFO: [Common 17-206] Exiting Vivado at Sat Nov 23 00:06:44 2019... diff --git a/end_game/end_game.runs/impl_1/main_clock_utilization_routed.rpt b/end_game/end_game.runs/impl_1/main_clock_utilization_routed.rpt new file mode 100644 index 0000000..4175bc4 --- /dev/null +++ b/end_game/end_game.runs/impl_1/main_clock_utilization_routed.rpt @@ -0,0 +1,193 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Sat Nov 23 00:06:33 2019 +| Host : DESKTOP-I2AH2G3 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file main_clock_utilization_routed.rpt +| Design : main +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.16 2016-11-09 +------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Device Cell Placement Summary for Global Clock g1 +8. Clock Region Cell Placement per Global Clock: Region X0Y0 +9. Clock Region Cell Placement per Global Clock: Region X1Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 2 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 69 | 0 | | | clk_out_BUFG_inst/O | clk_out_BUFG | +| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 2 | 55 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+-----------------------+-----------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+-----------------------+-----------------+ +| src0 | g0 | FDRE/Q | None | SLICE_X33Y45 | X0Y0 | 1 | 1 | | | clkDiv0/clk_out_reg/Q | clkDiv0/clk_out | +| src1 | g1 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+-----------------------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 34 | 1200 | 31 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 90 | 1500 | 42 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 1 | 2 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+--------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+--------------+ +| g0 | BUFG/O | n/a | | | | 69 | 0 | 0 | 0 | clk_out_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+--------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 69 | ++----+----+-----+ + + +7. Device Cell Placement Summary for Global Clock g1 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g1 | BUFG/O | n/a | | | | 55 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+-----+-----+ +| | X0 | X1 | ++----+-----+-----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 34 | 21 | ++----+-----+-----+ + + +8. Clock Region Cell Placement per Global Clock: Region X0Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g1 | n/a | BUFG/O | None | 34 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +9. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 69 | 0 | 69 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_out_BUFG | +| g1 | n/a | BUFG/O | None | 21 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_out_BUFG_inst] +set_property LOC BUFGCTRL_X0Y1 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y26 [get_ports clk] + +# Clock net "clk_out_BUFG" driven by instance "clk_out_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_out_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_out_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_out_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_out_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} +#endgroup + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y1" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} +#endgroup diff --git a/end_game/end_game.runs/impl_1/main_control_sets_placed.rpt b/end_game/end_game.runs/impl_1/main_control_sets_placed.rpt new file mode 100644 index 0000000..0604dc6 --- /dev/null +++ b/end_game/end_game.runs/impl_1/main_control_sets_placed.rpt @@ -0,0 +1,79 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Sat Nov 23 00:06:15 2019 +| Host : DESKTOP-I2AH2G3 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file main_control_sets_placed.rpt +| Design : main +| Device : xc7a35t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Flip-Flop Distribution +3. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 13 | +| Unused register locations in slices containing registers | 28 | ++----------------------------------------------------------+-------+ + + +2. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 15 | 6 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 33 | 8 | +| Yes | No | No | 42 | 13 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 34 | 16 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +3. Detailed Control Set Information +----------------------------------- + ++----------------+-----------------------------------------+-----------------------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+-----------------------------------------+-----------------------------------------+------------------+----------------+ +| clk_out_BUFG | | | 2 | 3 | +| clk_out_BUFG | dut0/cntrl0/FSM_onehot_stage[6]_i_2_n_0 | dut0/cntrl0/FSM_onehot_stage[6]_i_1_n_0 | 2 | 4 | +| clk_out_BUFG | dut0/cntrl0/instruction | dut0/cntrl0/instruction[7]_i_1_n_0 | 2 | 7 | +| clk_out_BUFG | dut0/cntrl0/pc_jmpaddr[7]_i_2_n_0 | dut0/cntrl0/pc_jmpaddr[7]_i_1_n_0 | 4 | 7 | +| clk_out_BUFG | dut0/cntrl0/regfile_data[7]_i_1_n_0 | dut0/cntrl0/instruction[7]_i_1_n_0 | 4 | 8 | +| clk_out_BUFG | dut0/cntrl0/E[0] | reset_IBUF | 4 | 8 | +| ~clk_out_BUFG | dut0/cntrl0/registerfile_reg[2][7][0] | | 2 | 8 | +| ~clk_out_BUFG | dut0/cntrl0/registerfile_reg[0][0][0] | | 2 | 8 | +| ~clk_out_BUFG | dut0/cntrl0/registerfile_reg[1][0][0] | | 2 | 8 | +| ~clk_out_BUFG | dut0/cntrl0/registerfile_reg[3][0][0] | | 2 | 8 | +| clk_IBUF_BUFG | seven_seg0/count[1]_i_1__0_n_0 | | 5 | 10 | +| clk_IBUF_BUFG | | | 4 | 12 | +| clk_IBUF_BUFG | | reset_IBUF | 8 | 33 | ++----------------+-----------------------------------------+-----------------------------------------+------------------+----------------+ + + ++--------+-----------------------+ +| Fanout | Number of ControlSets | ++--------+-----------------------+ +| 3 | 1 | +| 4 | 1 | +| 7 | 2 | +| 8 | 6 | +| 10 | 1 | +| 12 | 1 | +| 16+ | 1 | ++--------+-----------------------+ + + diff --git a/end_game/end_game.runs/impl_1/main_drc_opted.rpt b/end_game/end_game.runs/impl_1/main_drc_opted.rpt new file mode 100644 index 0000000..30e55d1 --- /dev/null +++ b/end_game/end_game.runs/impl_1/main_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Sat Nov 23 00:06:13 2019 +| Host : DESKTOP-I2AH2G3 running 64-bit major release (build 9200) +| Command : report_drc -file main_drc_opted.rpt +| Design : main +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/end_game/end_game.runs/impl_1/main_drc_routed.pb b/end_game/end_game.runs/impl_1/main_drc_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40 GIT binary patch literal 37 scmd;LGcqtV(KDRH% + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/end_game/end_game.runs/impl_1/main_drc_routed.rpx b/end_game/end_game.runs/impl_1/main_drc_routed.rpx new file mode 100644 index 0000000000000000000000000000000000000000..1bb28797b02214583f35befd6575152e059a0374 GIT binary patch literal 1626 zcmeHH&1=*^6i-;HB_bB3Q0nE;9;#AfcMDPq9^7oZtmtl8brnQHn!Kcg*_kjO+ufT- zkK(`O|KnBPBw5>3!L!gD<}mZ#@BKa=x$ij6>iXLH=8eu?`>DUbb^D|nPM8>@GPzdI z=-F$v{m$Kc(}?jfk#Q)6(U|zMm~Z@~@6MT9ICJN->wIzDudeg0b*ncHpa%G{Lip}l zYxCy2NOH!rt<~VT-<`aE+%SdX$qBPEax%Aa^?fgZl;sE) zkg3RXac(nL3$CO2q32oS!r!^nt1ydlgKhZG4CbQ;+vgNELj6vHYSx!*{{ynQQe|uB zAJ84^mGxkmIuV?)q_VAt9D##4MlqpRG31OT9o0e + Max violations: + Violations found: 124 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 124 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin clkDiv0/clk_out_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[32]/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#29 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#30 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#31 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#32 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#33 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#34 Warning +Non-clocked sequential cell +The clock pin clkDiv0/count_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#35 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/FSM_onehot_stage_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#36 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/FSM_onehot_stage_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#37 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/FSM_onehot_stage_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#38 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/FSM_onehot_stage_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#39 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/instruction_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#40 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/instruction_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#41 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/instruction_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#42 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/instruction_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#43 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/instruction_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#44 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/instruction_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#45 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/instruction_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#46 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jmpaddr_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#47 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jmpaddr_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#48 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jmpaddr_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#49 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jmpaddr_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#50 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jmpaddr_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#51 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jmpaddr_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#52 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jmpaddr_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#53 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jmpaddr_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#54 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/pc_jump_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#55 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_data_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#56 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_data_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#57 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_data_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#58 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_data_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#59 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_data_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#60 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_data_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#61 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_data_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#62 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_data_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#63 Warning +Non-clocked sequential cell +The clock pin dut0/cntrl0/regfile_regwrite_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#64 Warning +Non-clocked sequential cell +The clock pin dut0/pc0/data_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#65 Warning +Non-clocked sequential cell +The clock pin dut0/pc0/data_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#66 Warning +Non-clocked sequential cell +The clock pin dut0/pc0/data_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#67 Warning +Non-clocked sequential cell +The clock pin dut0/pc0/data_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#68 Warning +Non-clocked sequential cell +The clock pin dut0/pc0/data_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#69 Warning +Non-clocked sequential cell +The clock pin dut0/pc0/data_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#70 Warning +Non-clocked sequential cell +The clock pin dut0/pc0/data_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#71 Warning +Non-clocked sequential cell +The clock pin dut0/pc0/data_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#72 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[0][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#73 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[0][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#74 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[0][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#75 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[0][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#76 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[0][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#77 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[0][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#78 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[0][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#79 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[0][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#80 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[1][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#81 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[1][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#82 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[1][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#83 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[1][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#84 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[1][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#85 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[1][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#86 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[1][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#87 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[1][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#88 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[2][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#89 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[2][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#90 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[2][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#91 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[2][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#92 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[2][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#93 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[2][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#94 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[2][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#95 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[2][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#96 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[3][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#97 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[3][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#98 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[3][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#99 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[3][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#100 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[3][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#101 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[3][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#102 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[3][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#103 Warning +Non-clocked sequential cell +The clock pin dut0/reg0/registerfile_reg[3][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#104 Warning +Non-clocked sequential cell +The clock pin seven_seg0/Anode_Activate_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#105 Warning +Non-clocked sequential cell +The clock pin seven_seg0/Anode_Activate_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#106 Warning +Non-clocked sequential cell +The clock pin seven_seg0/Anode_Activate_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#107 Warning +Non-clocked sequential cell +The clock pin seven_seg0/Anode_Activate_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#108 Warning +Non-clocked sequential cell +The clock pin seven_seg0/LED_BCD_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#109 Warning +Non-clocked sequential cell +The clock pin seven_seg0/LED_BCD_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#110 Warning +Non-clocked sequential cell +The clock pin seven_seg0/LED_BCD_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#111 Warning +Non-clocked sequential cell +The clock pin seven_seg0/LED_BCD_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#112 Warning +Non-clocked sequential cell +The clock pin seven_seg0/count_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#113 Warning +Non-clocked sequential cell +The clock pin seven_seg0/count_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#114 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#115 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#116 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#117 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#118 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#119 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#120 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#121 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#122 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#123 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#124 Warning +Non-clocked sequential cell +The clock pin seven_seg0/mycounter_reg[9]/C is not reached by a timing clock +Related violations: + + diff --git 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All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Sat Nov 23 00:06:33 2019 +| Host : DESKTOP-I2AH2G3 running 64-bit major release (build 9200) +| Command : report_power -file main_power_routed.rpt -pb main_power_summary_routed.pb -rpx main_power_routed.rpx +| Design : main +| Device : xc7a35tcpg236-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+-------+ +| Total On-Chip Power (W) | 6.965 | +| Dynamic (W) | 6.861 | +| Device Static (W) | 0.104 | +| Effective TJA (C/W) | 5.0 | +| Max Ambient (C) | 50.2 | +| Junction Temperature (C) | 59.8 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+-------+ + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.346 | 355 | --- | --- | +| LUT as Logic | 0.300 | 163 | 20800 | 0.78 | +| Register | 0.023 | 124 | 41600 | 0.30 | +| CARRY4 | 0.017 | 10 | 8150 | 0.12 | +| BUFG | 0.006 | 2 | 32 | 6.25 | +| Others | 0.000 | 9 | --- | --- | +| Signals | 0.344 | 296 | --- | --- | +| I/O | 6.172 | 30 | 106 | 28.30 | +| Static Power | 0.104 | | | | +| Total | 6.965 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.734 | 0.698 | 0.036 | +| Vccaux | 1.800 | 0.241 | 0.226 | 0.015 | +| Vcco33 | 3.300 | 1.746 | 1.745 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 5.0 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++--------------+-----------+ +| Name | Power (W) | ++--------------+-----------+ +| main | 6.861 | +| clkDiv0 | 0.296 | +| dut0 | 0.247 | +| alu0 | <0.001 | +| cntrl0 | 0.047 | +| pc0 | 0.200 | +| reg0 | <0.001 | +| seven_seg0 | 0.119 | ++--------------+-----------+ + + diff --git a/end_game/end_game.runs/impl_1/main_power_routed.rpx b/end_game/end_game.runs/impl_1/main_power_routed.rpx new file mode 100644 index 0000000000000000000000000000000000000000..7144cf9170fffa3e27a4816e969e1cd6035a8ba1 GIT binary patch literal 101030 zcmeHwdw?8OmG|`IHB(7U(`+OJ15Gdzz;wE*y1J`+@_q@L7kTjrVHhTzWH2)mCo@QV zEJ2YK6hXjc!3Pi71^vLczz2f5ySTEet{^HdE9|nn?)v)Fb$y`j^8L=OM^{(Xy>+L% zF8dE+l9|rrcg{WcoO91P_i=(&;aS%rZDisn_jnLHSpaZ7D~ha;qh?^uH6w1>>YGj*1r4EWg#x;+klIUyDm9J zn?5!=G2Ykgd1C6o6fX)@4rJtX%eQ5v4z(M+?tC-VfYE#Zyx+Q-J zzBy^(`@6Lr+MLShlU0R4lX=V(_n1I zl5%Z{jvr|bYyQ+r^-_7sL&J}+w%$1J_EmPzs-D7oaH7GtBXC0d&)f*^&IFu)O%Ua(Ol2Fb3NDR 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All Rights Reserved. +----------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Sat Nov 23 00:06:15 2019 +| Host : DESKTOP-I2AH2G3 running 64-bit major release (build 9200) +| Command : report_utilization -file main_utilization_placed.rpt -pb main_utilization_placed.pb +| Design : main +| Device : 7a35tcpg236-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 163 | 0 | 20800 | 0.78 | +| LUT as Logic | 163 | 0 | 20800 | 0.78 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 124 | 0 | 41600 | 0.30 | +| Register as Flip Flop | 124 | 0 | 41600 | 0.30 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 8 | Yes | Set | - | +| 116 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 58 | 0 | 8150 | 0.71 | +| SLICEL | 34 | 0 | | | +| SLICEM | 24 | 0 | | | +| LUT as Logic | 163 | 0 | 20800 | 0.78 | +| using O5 output only | 0 | | | | +| using O6 output only | 116 | | | | +| using O5 and O6 | 47 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 59 | 0 | 20800 | 0.28 | +| fully used LUT-FF pairs | 25 | | | | +| LUT-FF pairs with one unused LUT output | 32 | | | | +| LUT-FF pairs with one unused Flip Flop | 33 | | | | +| Unique Control Sets | 13 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 30 | 30 | 106 | 28.30 | +| IOB Master Pads | 14 | | | | +| IOB Slave Pads | 15 | | | | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 2 | 0 | 32 | 6.25 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 116 | Flop & Latch | +| LUT2 | 56 | LUT | +| LUT6 | 55 | LUT | +| LUT5 | 32 | LUT | +| LUT4 | 32 | LUT | +| LUT3 | 32 | LUT | +| OBUF | 27 | IO | +| CARRY4 | 10 | CarryLogic | +| FDSE | 8 | Flop & Latch | +| LUT1 | 3 | LUT | +| IBUF | 3 | IO | +| BUFG | 2 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/end_game/end_game.runs/impl_1/opt_design.pb b/end_game/end_game.runs/impl_1/opt_design.pb new file mode 100644 index 0000000000000000000000000000000000000000..2d843ef42869b44eefd3e0314a4ff21e940ed6a0 GIT binary patch literal 7079 zcmc&(U2hvj6s?mufg!3&MO#QK7*R|UtG0J$*Y?`95;O^=g{o1Ss+ENlZFk4^lJ)Mg zGtLL9Y0Z;*NjK{0 zaDUGs?S3Gp3oj4h5$&A9Ye0DU{d|I^k8W@FeP1HEwz-Ne4oHR(vjg98B@hx{2@-%f zAdu2&2%IxYl%@gMM3>PMVMQ@}1&+5Yz7rEdG`;v9EX+k@xxV1^8k&WelrWnmcsf0+ zI7w)$s1mU-h(K$RjhCaozb!Xqi6A!3^j_gumHV+a#S@Z)k{=LX2{8pXbGkO)IpJgIhgltn{nRmd)`5uLbQ=) zKu4dPurtM~K#MU#%Tshk3ZU)!F7LvkhdYrwn5A`ETnMA!2WAU;1HGf+^(YD=B|@ZR z)JS?a4!XDDF$*#?Vr>>lL5VJl)s}<}WDJRkNx;1Ta@X~Nk6xUO<-;h9VHB;rTt{wT zh}y3?G>76EGpZtvwzu3K!^?c7iS4kD?_y1B%0Gg?z|6Bk4%;0LYGuRFa2Y>h5XAvr zesm9h7BXuG9;r4O<*K2>&pMz`7$92NB#J_iR^~b?tOY*9oQYWS&(~J5aCT&kl!^NaDhNZlZRyO*v+CcBFzsn-QBH&4C1V+5Ta&YMS zFp|L2FpIO0pE8q3b_F?XW`|qzIw=v|OhfrCx;BUuxR=SsJa4#+(HJhHDdx+=e8xx- zy@PHgm=Qdf7Qe)+aTV$JnwT^i%rKmG9kO>&)YCXjFI`P7U5%P!q)SNED4VsEcD1sm zDYlo63(l_cKn&Q1iYBYkAzE-yz>yF^mh7em<7!c>C-@z!2g#OVc?#mv4F&3wMco{M zy+4^&sYx)L6cN^DYRj&hbfdR=QPfS&f8Bx8EQ=;e%pT^rNC9TGcYlTI1YB zH@05Bk?8(Bo#-YeRtm756`B+vnNWc3$pomY1o#okKiOj}%toN9lnwM*LcEUSUyU-| z(1~rw=Li%&~Z83XC}LZjp*PpY9>0U z;$!A|TZ+)nQW1ZjP7%|heR^$7bqj|>+J~OW-F3x5avvO9?nk=Wv%3&NlcVls-so(8 zh^p&g3_$CW?Jwd+{%vWpdX~GKisFr6Z_*qep_rrkGuQJl-*H21dx5M|PSH)-%6ng0HHdV)^bdzE?hNvJt`c{Q3d^@OOS@F~BXrWrGm5Hvn zTA*5q zn2nLdzKgC7=6Sxh{xyyQc-HU4Q_NBVUP^j~d6)qP(_QyNbW=3}*dbu)fNFgvWEB7l zn`#ZkY?^G6haStg*?7oocXT#zoE5QY>DhicPqnO|D{|uu$GE|JgV_H(UN)+_M?rRn z79W@#hQbq)R@E`mfzD!#JE9WKKRJZAz|n+Uh~GDWdxl>y=EHjlpGDF$0k*(Jtx+;C zf8=YA*kld^aJm)ZeTZtS&B{~GB3|i+73MqJ9jnKNAIjig^NI@yZIen5%*buXv$A8W z+Q|iYDFObM)Y#B0?Ve1kOtDnwV? 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All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/SDK/2017.1/bin;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.1/bin;"; +} else { + PathVal = "C:/Xilinx/SDK/2017.1/bin;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log main.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source main.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/end_game/end_game.runs/impl_1/runme.bat b/end_game/end_game.runs/impl_1/runme.bat new file mode 100644 index 0000000..570480c --- /dev/null +++ b/end_game/end_game.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/end_game/end_game.runs/impl_1/runme.log b/end_game/end_game.runs/impl_1/runme.log new file mode 100644 index 0000000..ac6b456 --- /dev/null +++ b/end_game/end_game.runs/impl_1/runme.log @@ -0,0 +1,405 @@ + +*** Running vivado + with args -log main.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source main.tcl -notrace + + +****** Vivado v2017.1 (64-bit) + **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017 + **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source main.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/hp/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc] +Finished Parsing XDC File [C:/Users/hp/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 588.727 ; gain = 286.953 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +INFO: [DRC 23-27] Running DRC with 2 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.440 . Memory (MB): peak = 599.543 ; gain = 10.816 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 1 inverter(s) to 8 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 199e44df7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 34 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1105a4869 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 7 cells and removed 14 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1931c868d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1931c868d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1931c868d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1931c868d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 132bfa9e8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1154.863 ; gain = 0.000 +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1154.863 ; gain = 566.137 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/hp/end_game/end_game.runs/impl_1/main_opt.dcp' has been generated. +Command: report_drc -file main_drc_opted.rpt +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/hp/end_game/end_game.runs/impl_1/main_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +INFO: [DRC 23-27] Running DRC with 2 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +INFO: [DRC 23-27] Running DRC with 2 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 121ed6241 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1643462e3 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.669 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 22f440c62 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.686 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 22f440c62 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.688 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 22f440c62 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.688 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1712aec50 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.870 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1712aec50 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.873 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 206c29ca8 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.881 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 28653ff41 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.888 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 28653ff41 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.889 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 2583ee500 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1d3680a9f + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d3680a9f + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Ending Placer Task | Checksum: 114cef4fc + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1154.863 ; gain = 0.000 +36 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 1154.863 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/hp/end_game/end_game.runs/impl_1/main_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1154.863 ; gain = 0.000 +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1154.863 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1154.863 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +INFO: [DRC 23-27] Running DRC with 2 threads +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: e7fcca7e ConstDB: 0 ShapeSum: 2cd22a7e RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 170549879 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1248.793 ; gain = 93.930 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 170549879 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1254.777 ; gain = 99.914 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 170549879 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1254.777 ; gain = 99.914 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 10d7fb730 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: e1814700 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 27 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 +Phase 4 Rip-up And Reroute | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 +Phase 6 Post Hold Fix | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0762975 % + Global Horizontal Routing Utilization = 0.107236 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions. +Phase 7 Route finalize | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.539 ; gain = 105.676 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 122ad0ef8 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.766 ; gain = 105.902 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: ca204202 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.766 ; gain = 105.902 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.766 ; gain = 105.902 + +Routing Is Done. +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 1260.766 ; gain = 105.902 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1260.766 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/hp/end_game/end_game.runs/impl_1/main_routed.dcp' has been generated. +Command: report_drc -file main_drc_routed.rpt -pb main_drc_routed.pb -rpx main_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/hp/end_game/end_game.runs/impl_1/main_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file main_methodology_drc_routed.rpt -rpx main_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/hp/end_game/end_game.runs/impl_1/main_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file main_power_routed.rpt -pb main_power_summary_routed.pb -rpx main_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +51 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +Command: write_bitstream -force main.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' +Running DRC as a precondition to command write_bitstream +Command: report_drc (run_mandatory_drcs) for: bitstream_checks +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./main.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). +61 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1702.137 ; gain = 405.188 +INFO: [Common 17-206] Exiting Vivado at Sat Nov 23 00:06:44 2019... diff --git a/end_game/end_game.runs/impl_1/runme.sh b/end_game/end_game.runs/impl_1/runme.sh new file mode 100644 index 0000000..67a85ca --- /dev/null +++ b/end_game/end_game.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/SDK/2017.1/bin;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2017.1/bin +else + PATH=C:/Xilinx/SDK/2017.1/bin;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2017.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/hp/end_game/end_game.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log main.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source main.tcl -notrace + + diff --git a/end_game/end_game.runs/impl_1/usage_statistics_webtalk.html b/end_game/end_game.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..dc1b8ca --- /dev/null +++ b/end_game/end_game.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,694 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version1846317
date_generatedSat Nov 23 00:06:43 2019os_platformWIN64
product_versionVivado v2017.1 (64-bit)project_idbbee60fc56e8409db2cdf5ab01427605
project_iteration4random_ida20516f5-6568-4922-95cb-fd63966b3ff7
registration_id211458424_1777531420_210673176_760route_designTRUE
target_devicexc7a35ttarget_familyartix7
target_packagecpg236target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-6700 CPU @ 3.40GHzcpu_speed3408 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram17.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
gui_resources
addsrcwizard_specify_or_create_constraint_files=1addsrcwizard_specify_simulation_specific_hdl_files=1basedialog_cancel=10basedialog_ok=14
constraintschooserpanel_create_file=1createconstraintsfilepanel_file_name=1filesetpanel_file_set_panel_tree=100flownavigatortreepanel_flow_navigator_tree=75
graphicalview_zoom_fit=8graphicalview_zoom_in=32graphicalview_zoom_out=17hcodeeditor_blank_operations=17
hcodeeditor_commands_to_fold_text=7hcodeeditor_diff_with=13mainmenumgr_file=2pacommandnames_add_sources=1
pacommandnames_auto_connect_target=3pacommandnames_auto_update_hier=2pacommandnames_open_project=1pacommandnames_simulation_run_behavioral=16
pacommandnames_toggle_view_nav=5paviews_code=10planaheadtab_show_flow_navigator=5programdebugtab_open_recently_opened_target=1
programfpgadialog_program=5progressdialog_cancel=1rdicommands_cut=1rdiviews_waveform_viewer=22
saveprojectutils_save=1srcmenu_ip_hierarchy=4stalerundialog_open_design=1syntheticagettingstartedview_recent_projects=2
syntheticastatemonitor_cancel=2taskbanner_close=3tclconsoleview_tcl_console_code_editor=2
+ + + + + + + + + + + + + + + + + + + + + +
java_command_handlers
addsources=1autoconnecttarget=3closeproject=1editundo=1
launchprogramfpga=5openhardwaremanager=9openproject=1openrecenttarget=3
programdevice=5runbitgen=9runschematic=1runsynthesis=4
savefileproxyhandler=1showview=1simulationrun=16toggleviewnavigator=5
viewtaskimplementation=1viewtasksynthesis=1waveformsaveconfiguration=1
+ + + +
other_data
guimode=3
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=20simulator_language=Verilogsrcsetcount=9synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + + + + + +
post_unisim_transformation
bufg=2carry4=10fdre=119fdse=8
gnd=6ibuf=3lut1=36lut2=55
lut3=33lut4=31lut5=36lut6=57
obuf=27vcc=3
+
+ + + + + + + + + + + + + + + + +
pre_unisim_transformation
bufg=2carry4=10fdre=119fdse=8
gnd=6ibuf=3lut1=36lut2=55
lut3=33lut4=31lut5=36lut6=57
obuf=27vcc=3
+

+ + + + +
report_drc
+ + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-ruledecks=default::[not_specified]-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
cfgbvs-1=1
+

+ + + + +
report_methodology
+ + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-waived=default::[not_specified]
+
+ + + +
results
timing-17=124
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-l=default::[not_specified]-name=default::[not_specified]-no_propagation=default::[not_specified]
-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]-vid=default::[not_specified]
-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")confidence_level_clock_activity=Lowconfidence_level_design_state=High
confidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=Lowconfidence_level_overall=Low
customer=TBDcustomer_class=TBDdevstatic=0.104141die=xc7a35tcpg236-1
dsp_output_toggle=12.500000dynamic=6.861038effective_thetaja=5.0enable_probability=0.990000
family=artix7ff_toggle=12.500000flow_state=routedheatsink=medium (Medium Profile)
i/o=6.171810input_toggle=12.500000junction_temp=59.8 (C)logic=0.345639
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=6.965179output_enable=1.000000
output_load=5.000000output_toggle=12.500000package=cpg236pct_clock_constrained=1.000000
pct_inputs_defined=0platform=nt64process=typicalram_enable=50.000000
ram_write=50.000000read_saif=Falseset/reset_probability=0.000000signal_rate=False
signals=0.343589simulation_file=Nonespeedgrade=-1static_prob=False
temp_grade=commercialthetajb=7.5 (C/W)thetasa=4.6 (C/W)toggle_rate=False
user_board_temp=25.0 (C)user_effective_thetaja=5.0user_junc_temp=59.8 (C)user_thetajb=7.5 (C/W)
user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000
vccadc_voltage=1.800000vccaux_dynamic_current=0.225856vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.015387vccaux_total_current=0.241244
vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.000701vccbram_total_current=0.000701
vccbram_voltage=1.000000vccint_dynamic_current=0.697548vccint_static_current=0.036443vccint_total_current=0.733991
vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000
vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000
vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000
vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000
vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000
vcco25_voltage=2.500000vcco33_dynamic_current=1.744530vcco33_static_current=0.001000vcco33_total_current=1.745530
vcco33_voltage=3.300000version=2017.1
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=2bufgctrl_util_percentage=6.25
bufhce_available=72bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=20bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=10bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=20bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=5mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=5plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=90dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=50block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=100ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=50ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=2carry4_functional_category=CarryLogiccarry4_used=10
fdre_functional_category=Flop & Latchfdre_used=116fdse_functional_category=Flop & Latchfdse_used=8
ibuf_functional_category=IOibuf_used=3lut1_functional_category=LUTlut1_used=3
lut2_functional_category=LUTlut2_used=56lut3_functional_category=LUTlut3_used=32
lut4_functional_category=LUTlut4_used=32lut5_functional_category=LUTlut5_used=32
lut6_functional_category=LUTlut6_used=55obuf_functional_category=IOobuf_used=27
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=16300f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=8150f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=163lut_as_logic_util_percentage=0.78
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600register_as_flip_flop_fixed=0register_as_flip_flop_used=124register_as_flip_flop_util_percentage=0.30
register_as_latch_available=41600register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=20800slice_luts_fixed=0slice_luts_used=163slice_luts_util_percentage=0.78
slice_registers_available=41600slice_registers_fixed=0slice_registers_used=124slice_registers_util_percentage=0.30
fully_used_lut_ff_pairs_fixed=0.30fully_used_lut_ff_pairs_used=25lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=163lut_as_logic_util_percentage=0.78
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=33
lut_ff_pairs_with_one_unused_lut_output_fixed=33lut_ff_pairs_with_one_unused_lut_output_used=32lut_flip_flop_pairs_available=20800lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=59lut_flip_flop_pairs_util_percentage=0.28slice_available=8150slice_fixed=0
slice_used=58slice_util_percentage=0.71slicel_fixed=0slicel_used=34
slicem_fixed=0slicem_used=24unique_control_sets_used=13using_o5_and_o6_fixed=13
using_o5_and_o6_used=47using_o5_output_only_fixed=47using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=116
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + +
usage
actual_expansions=340619bogomips=0bram18=0bram36=0
bufg=0bufr=0ctrls=13dsp=0
effort=2estimated_expansions=295698ff=124global_clocks=2
high_fanout_nets=0iob=30lut=164movable_instances=385
nets=427pins=1912pll=0router_runtime=0.000000
router_timing_driven=1threads=2timing_constraints_exist=1
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a35tcpg236-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=main-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:26shls_ip=0memory_gain=482.645MBmemory_peak=776.656MB
+

+ + + +
xsim
+ + + + +
command_line_options
-sim_mode=default::behavioral-sim_type=default::
+

+ + diff --git a/end_game/end_game.runs/impl_1/usage_statistics_webtalk.xml b/end_game/end_game.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..c2a4706 --- /dev/null +++ b/end_game/end_game.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,623 @@ + + +
+
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+
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+
+
+ diff --git a/end_game/end_game.runs/impl_1/vivado.jou b/end_game/end_game.runs/impl_1/vivado.jou new file mode 100644 index 0000000..b6966b5 --- /dev/null +++ b/end_game/end_game.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.1 (64-bit) +# SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017 +# IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 +# Start of session at: Sat Nov 23 00:05:51 2019 +# Process ID: 4936 +# Current directory: C:/Users/hp/end_game/end_game.runs/impl_1 +# Command line: vivado.exe -log main.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source main.tcl -notrace +# Log file: C:/Users/hp/end_game/end_game.runs/impl_1/main.vdi +# Journal file: C:/Users/hp/end_game/end_game.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source main.tcl -notrace diff --git a/end_game/end_game.runs/impl_1/vivado.pb b/end_game/end_game.runs/impl_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..7ab450d5c7c13b9b7533b51e0aaa3488447f2a79 GIT binary patch literal 149 zcmd;TVB`{Ut;j6N%u82LEmlY@0g`%pdRzjmQp`pMW?F2?`MJ6Ic}7xPY+;#Yi7EL; z>?x^fiKRIuRxpN<4wpnQP@`XdnSznAf`NgRfti(wiGq=Vp(Up3C^kcLU7*Ps3a+1emz^xVT*NQWSzxlkh-E1OLT(jNWevMyGiANIotXtw z^{H=t>vMlXe@I{Yr+Q{~ZPwT=$wMU`?D5RGeCIpgIUpCUw1eT0`fdxaNtDm6W^0w= zopXLp-9R}Wsh~#}f-BZL;YupO=n$9sfp8ceQtp@Glq|cfPa{vY#vhIst0mj6oZbp^ zqulSATlp;dGlRZ+tP~rDiu(hs0z6;}Q|xhv`I2EUiTjMINHDy2UwZAgdFo_X}?k!n3XaDZFh6Z*jC3qd7vGN0IMqBzKS6m`Xr06wC>Hmunz2z8WL| zF{x_Ku2i>+cS4W)k53tO$rtFuYjvH2%(6{N`e7QHpKoGJ7u5s{1EG4ZaBx9HeoqHN zRUj_)k=)SLZs7@`dd?|x&g2~bvphOP57L=maCHh9Vs#44bb-H%t65SlE`S?y4`s+a zo1{`Ay4Vvm|6W4BEC4BRJ-o{#ANcrC1R)cO zGuguX4E!?z?%DXE52U^J@I3Go9Wbbnd3lMs#1h!gp-%A7iG%ptHZbIWL84*Nyi8yn{*LPReQG zZ&Sw@2v?^VKrbpLhTLZ+?C#dVRajA|3vRkt8x6TH^-~kO1u1nQTSz(@4472R)z)Ol z9NxdwwxItLAR|))ZDM^7s0^5!_P@e>9rq*OF&t0e>%8jflwGdV@BrKx)$e!PxX(R? zuT1s>&kHVek>w>Q#;Apm2Cg@$OH%uD>P5`PZ>J0M1HxZiK(QH4euspTs8g`dn4IR2 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rfile:../../../end_game.srcs/constrs_1/new/my_constraint.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W5 [get_ports clk] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W7 [get_ports {data[6]}] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W6 [get_ports {data[5]}] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U8 [get_ports {data[4]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V8 [get_ports {data[3]}] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U5 [get_ports {data[2]}] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V5 [get_ports {data[1]}] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U7 [get_ports {data[0]}] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U2 [get_ports {anode[0]}] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U4 [get_ports {anode[1]}] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V4 [get_ports {anode[2]}] +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W4 [get_ports {anode[3]}] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U16 [get_ports {datamem_address[0]}] +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E19 [get_ports {datamem_address[1]}] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U19 [get_ports {datamem_address[2]}] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V19 [get_ports {datamem_address[3]}] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W18 [get_ports {datamem_address[4]}] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U15 [get_ports {datamem_address[5]}] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U14 [get_ports {datamem_address[6]}] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V14 [get_ports {datamem_address[7]}] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V13 [get_ports {idata[0]}] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V3 [get_ports {idata[1]}] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W3 [get_ports {idata[2]}] +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U3 [get_ports {idata[3]}] +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports {idata[4]}] +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN N3 [get_ports {idata[5]}] +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P1 [get_ports {idata[6]}] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN L1 [get_ports {idata[7]}] +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T18 [get_ports interrupt] +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V16 [get_ports reset] diff --git a/end_game/end_game.runs/synth_1/ISEWrap.js b/end_game/end_game.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..8284d2d --- /dev/null +++ b/end_game/end_game.runs/synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/end_game/end_game.runs/synth_1/ISEWrap.sh b/end_game/end_game.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/end_game/end_game.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/end_game/end_game.runs/synth_1/_Vivado_Synthesis.queue.rst b/end_game/end_game.runs/synth_1/_Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/synth_1/_vivado.begin.rst b/end_game/end_game.runs/synth_1/_vivado.begin.rst new file mode 100644 index 0000000..7629f05 --- /dev/null +++ b/end_game/end_game.runs/synth_1/_vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/end_game/end_game.runs/synth_1/_vivado.end.rst b/end_game/end_game.runs/synth_1/_vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/end_game/end_game.runs/synth_1/fsm_encoding.os b/end_game/end_game.runs/synth_1/fsm_encoding.os new file mode 100644 index 0000000..1b73771 --- /dev/null +++ b/end_game/end_game.runs/synth_1/fsm_encoding.os @@ -0,0 +1,5 @@ + + add_fsm_encoding \ + {control.stage} \ + { } \ + {{000 0000010} {001 0000100} {010 0000001} {011 1000000} {100 0010000} {101 0001000} {110 0100000} } diff --git a/end_game/end_game.runs/synth_1/gen_run.xml b/end_game/end_game.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..0f18d71 --- /dev/null +++ b/end_game/end_game.runs/synth_1/gen_run.xml @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/end_game/end_game.runs/synth_1/htr.txt b/end_game/end_game.runs/synth_1/htr.txt new file mode 100644 index 0000000..707aa40 --- /dev/null +++ b/end_game/end_game.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. 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To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v:14] +INFO: [Synth 8-802] inferred FSM for state register 'stage_reg' in module 'control' +WARNING: [Synth 8-6014] Unused sequential element stage_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:42] +INFO: [Synth 8-5544] ROM "regfile_regwrite" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "regfile_regwrite" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "pc_jump" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "pc_jmpaddr" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "stage" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "stage" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "usermem_address" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "usermem_data_out" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "regfile_data" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "pc_jmpaddr" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "stage" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "stage" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5545] ROM "clk_out" won't be mapped to RAM because address size (33) is larger than maximum supported(25) +WARNING: [Synth 8-6014] Unused sequential element stage_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:42] +WARNING: [Synth 8-6014] Unused sequential element stage_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:42] +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE1 | 0000001 | 010 + iSTATE | 0000010 | 000 + iSTATE0 | 0000100 | 001 + iSTATE5 | 0001000 | 101 + iSTATE3 | 0010000 | 100 + iSTATE4 | 0100000 | 110 +* + iSTATE2 | 1000000 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'stage_reg' using encoding 'one-hot' in module 'control' +WARNING: [Synth 8-6014] Unused sequential element stage_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:42] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 750.871 ; gain = 454.805 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 33 Bit Adders := 1 + 2 Input 11 Bit Adders := 1 + 2 Input 8 Bit Adders := 3 + 3 Input 8 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 ++---XORs : + 2 Input 8 Bit XORs := 1 ++---Registers : + 33 Bit Registers := 1 + 11 Bit Registers := 1 + 8 Bit Registers := 15 + 4 Bit Registers := 2 + 2 Bit Registers := 1 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 33 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 16 + 4 Input 8 Bit Muxes := 3 + 8 Input 8 Bit Muxes := 2 + 6 Input 8 Bit Muxes := 3 + 3 Input 8 Bit Muxes := 2 + 21 Input 7 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 2 + 7 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 52 + 6 Input 1 Bit Muxes := 9 + 3 Input 1 Bit Muxes := 11 + 4 Input 1 Bit Muxes := 11 + 7 Input 1 Bit Muxes := 1 + 5 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module sram +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 8 +Module seven_seg +Detailed RTL Component Info : ++---Adders : + 2 Input 11 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 ++---Registers : + 11 Bit Registers := 1 + 4 Bit Registers := 2 + 2 Bit Registers := 1 ++---Muxes : + 4 Input 4 Bit Muxes := 2 +Module pc +Detailed RTL Component Info : ++---Adders : + 2 Input 8 Bit Adders := 1 ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module regfile +Detailed RTL Component Info : ++---Muxes : + 4 Input 8 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 4 +Module alu +Detailed RTL Component Info : ++---Adders : + 3 Input 8 Bit Adders := 1 ++---XORs : + 2 Input 8 Bit XORs := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 2 + 8 Input 8 Bit Muxes := 2 +Module control +Detailed RTL Component Info : ++---Adders : + 2 Input 8 Bit Adders := 2 ++---Registers : + 8 Bit Registers := 6 + 1 Bit Registers := 3 ++---Muxes : + 4 Input 8 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 11 + 6 Input 8 Bit Muxes := 3 + 3 Input 8 Bit Muxes := 2 + 21 Input 7 Bit Muxes := 1 + 7 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 47 + 6 Input 1 Bit Muxes := 9 + 3 Input 1 Bit Muxes := 11 + 4 Input 1 Bit Muxes := 11 + 7 Input 1 Bit Muxes := 1 + 5 Input 1 Bit Muxes := 3 +Module clkDiv +Detailed RTL Component Info : ++---Adders : + 2 Input 33 Bit Adders := 1 ++---Registers : + 33 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 33 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6014] Unused sequential element dut0/cntrl0/usermem_data_out_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:48] +WARNING: [Synth 8-6014] Unused sequential element dut0/cntrl0/usermem_address_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:48] +WARNING: [Synth 8-6014] Unused sequential element dut0/cntrl0/rw_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:49] +INFO: [Synth 8-5545] ROM "clkDiv0/clk_out" won't be mapped to RAM because address size (33) is larger than maximum supported(25) +WARNING: [Synth 8-6014] Unused sequential element seven_seg0/mycounter_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v:122] +WARNING: [Synth 8-6014] Unused sequential element dut0/pc0/data_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v:7] +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][0]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][0]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][0]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][1]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][1]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][2]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][3]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][4]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][6]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][6]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][7]' (FD) to 'sram0/memory_array_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][7]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][7]' (FD) to 'sram0/memory_array_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][7]' (FD) to 'sram0/memory_array_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][7]' (FD) to 'sram0/memory_array_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][7]' (FD) to 'sram0/memory_array_reg[2][7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sram0/memory_array_reg[3][7] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sram0/memory_array_reg[2][7] ) +WARNING: [Synth 8-3332] Sequential element (sram0/memory_array_reg[3][7]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (sram0/memory_array_reg[2][7]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/instruction_reg[5]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[7]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[6]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[5]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[4]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[3]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[2]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[1]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[0]) is unused and will be removed from module main. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 750.871 ; gain = 454.805 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 751.156 ; gain = 455.090 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 751.453 ; gain = 455.387 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 2| +|2 |CARRY4 | 10| +|3 |LUT1 | 36| +|4 |LUT2 | 55| +|5 |LUT3 | 33| +|6 |LUT4 | 31| +|7 |LUT5 | 36| +|8 |LUT6 | 57| +|9 |FDRE | 119| +|10 |FDSE | 8| +|11 |IBUF | 3| +|12 |OBUF | 27| ++------+-------+------+ + +Report Instance Areas: ++------+-------------+----------+------+ +| |Instance |Module |Cells | ++------+-------------+----------+------+ +|1 |top | | 417| +|2 | clkDiv0 |clkDiv | 116| +|3 | dut0 |cpu | 221| +|4 | alu0 |alu | 2| +|5 | cntrl0 |control | 101| +|6 | pc0 |pc | 55| +|7 | reg0 |regfile | 63| +|8 | seven_seg0 |seven_seg | 48| ++------+-------------+----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 22 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 776.656 ; gain = 157.512 +Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +117 Infos, 153 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 776.656 ; gain = 483.043 +INFO: [Common 17-1381] The checkpoint 'C:/Users/hp/end_game/end_game.runs/synth_1/main.dcp' has been generated. +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 776.656 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sat Nov 23 00:05:44 2019... diff --git a/end_game/end_game.runs/synth_1/main_utilization_synth.pb b/end_game/end_game.runs/synth_1/main_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..e9bf27f88e9fabd18af3064b5d155bfd2212d2c4 GIT binary patch literal 276 zcmd;LGcqtV*E5{NtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z=QNj>p+U+0DeqCgId*S_7#KXA_X;yKEOKiVDN8E1@0DZ#g1bOc%x$R@h`m;x zf#HMWUm$tK>8OHp)+5KWsvz;XY77h>PEUa(14FM7h`b9Vw>T{|2C> b`Akyim zB?H3=he=i(PN8n@&LKfQXYD{r=GrqbEO2-VBpDdqx`4>Nt{{WKK#W literal 0 HcmV?d00001 diff --git a/end_game/end_game.runs/synth_1/main_utilization_synth.rpt b/end_game/end_game.runs/synth_1/main_utilization_synth.rpt new file mode 100644 index 0000000..4c0995a --- /dev/null +++ b/end_game/end_game.runs/synth_1/main_utilization_synth.rpt @@ -0,0 +1,182 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Sat Nov 23 00:05:44 2019 +| Host : DESKTOP-I2AH2G3 running 64-bit major release (build 9200) +| Command : report_utilization -file main_utilization_synth.rpt -pb main_utilization_synth.pb +| Design : main +| Device : 7a35tcpg236-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 201 | 0 | 20800 | 0.97 | +| LUT as Logic | 201 | 0 | 20800 | 0.97 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 127 | 0 | 41600 | 0.31 | +| Register as Flip Flop | 127 | 0 | 41600 | 0.31 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 8 | Yes | Set | - | +| 119 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 30 | 0 | 106 | 28.30 | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 2 | 0 | 32 | 6.25 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 119 | Flop & Latch | +| LUT6 | 57 | LUT | +| LUT2 | 55 | LUT | +| LUT5 | 36 | LUT | +| LUT1 | 36 | LUT | +| LUT3 | 33 | LUT | +| LUT4 | 31 | LUT | +| OBUF | 27 | IO | +| CARRY4 | 10 | CarryLogic | +| FDSE | 8 | Flop & Latch | +| IBUF | 3 | IO | +| BUFG | 2 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/end_game/end_game.runs/synth_1/rundef.js b/end_game/end_game.runs/synth_1/rundef.js new file mode 100644 index 0000000..7356a5c --- /dev/null +++ b/end_game/end_game.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/SDK/2017.1/bin;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.1/bin;"; +} else { + PathVal = "C:/Xilinx/SDK/2017.1/bin;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log main.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source main.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/end_game/end_game.runs/synth_1/runme.bat b/end_game/end_game.runs/synth_1/runme.bat new file mode 100644 index 0000000..570480c --- /dev/null +++ b/end_game/end_game.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/end_game/end_game.runs/synth_1/runme.log b/end_game/end_game.runs/synth_1/runme.log new file mode 100644 index 0000000..a0a6a0c --- /dev/null +++ b/end_game/end_game.runs/synth_1/runme.log @@ -0,0 +1,639 @@ + +*** Running vivado + with args -log main.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source main.tcl + + +****** Vivado v2017.1 (64-bit) + **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017 + **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source main.tcl -notrace +Command: synth_design -top main -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t-cpg236' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t-cpg236' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 836 +WARNING: [Synth 8-2611] redeclaration of ansi port clk is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:24] +WARNING: [Synth 8-2611] redeclaration of ansi port reset is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:24] +WARNING: [Synth 8-2611] redeclaration of ansi port interrupt is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:24] +WARNING: [Synth 8-2611] redeclaration of ansi port datamem_address is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:25] +WARNING: [Synth 8-2611] redeclaration of ansi port idata is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:25] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 394.164 ; gain = 98.098 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'main' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:23] +INFO: [Synth 8-638] synthesizing module 'sram' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:23] +INFO: [Synth 8-4471] merging register 'memory_array_reg[5][7:0]' into 'memory_array_reg[3][7:0]' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:32] +WARNING: [Synth 8-6014] Unused sequential element memory_array_reg[5] was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:32] +WARNING: [Synth 8-3848] Net memory_array[0] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[1] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[11] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[12] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[13] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[14] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[15] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[16] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[17] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[18] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[19] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[20] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[21] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[22] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[23] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[24] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[25] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[26] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[27] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[28] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[29] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[30] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[31] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[32] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[33] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[34] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[35] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[36] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[37] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[38] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[39] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[40] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[41] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[42] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[43] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[44] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[45] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[46] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[47] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[48] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[49] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[50] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[51] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[52] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[53] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[54] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[55] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[56] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[57] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[58] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[59] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[60] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[61] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[62] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[63] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[64] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[65] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[66] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[67] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[68] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[69] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[70] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[71] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[72] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[73] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[74] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[75] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[76] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[77] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[78] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[79] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[80] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[81] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[82] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[83] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[84] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[85] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[86] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[87] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[88] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[89] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[90] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[91] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[92] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[93] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[94] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[95] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[96] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[97] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[98] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[99] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[100] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[101] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[102] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[103] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[104] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[105] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[106] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[107] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +WARNING: [Synth 8-3848] Net memory_array[108] in module/entity sram does not have driver. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:29] +INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-256] done synthesizing module 'sram' (1#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v:23] +INFO: [Synth 8-638] synthesizing module 'seven_seg' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v:110] +INFO: [Synth 8-256] done synthesizing module 'seven_seg' (2#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v:110] +INFO: [Synth 8-638] synthesizing module 'cpu' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v:1] +INFO: [Synth 8-638] synthesizing module 'pc' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v:1] +INFO: [Synth 8-256] done synthesizing module 'pc' (3#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v:1] +INFO: [Synth 8-638] synthesizing module 'regfile' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/reg.v:2] +INFO: [Synth 8-256] done synthesizing module 'regfile' (4#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/reg.v:2] +INFO: [Synth 8-638] synthesizing module 'alu' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v:1] +INFO: [Synth 8-256] done synthesizing module 'alu' (5#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v:1] +INFO: [Synth 8-638] synthesizing module 'control' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:1] + Parameter state0 bound to: 3'b000 + Parameter state1 bound to: 3'b001 + Parameter state2 bound to: 3'b010 + Parameter state3 bound to: 3'b011 + Parameter state4 bound to: 3'b100 + Parameter state5 bound to: 3'b101 + Parameter state6 bound to: 3'b110 +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:151] +INFO: [Synth 8-256] done synthesizing module 'control' (6#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:1] +INFO: [Synth 8-256] done synthesizing module 'cpu' (7#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v:1] +INFO: [Synth 8-638] synthesizing module 'clkDiv' [C:/Users/hp/end_game/end_game.srcs/sources_1/new/clock_div.v:1] +INFO: [Synth 8-256] done synthesizing module 'clkDiv' (8#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/clock_div.v:1] +WARNING: [Synth 8-350] instance 'clkDiv0' of module 'clkDiv' requires 5 connections, but only 3 given [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:44] +INFO: [Synth 8-256] done synthesizing module 'main' (9#1) [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:23] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value1[7] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value1[6] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value1[5] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value1[4] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value1[3] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value1[2] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value1[1] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value1[0] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value2[7] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value2[6] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value2[5] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value2[4] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value2[3] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value2[2] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value2[1] +WARNING: [Synth 8-3331] design clkDiv has unconnected port value2[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 427.793 ; gain = 131.727 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +WARNING: [Synth 8-3295] tying undriven pin dut0:usermem_data_in[7] to constant 0 [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:32] +WARNING: [Synth 8-3295] tying undriven pin dut0:usermem_data_in[6] to constant 0 [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:32] +WARNING: [Synth 8-3295] tying undriven pin dut0:usermem_data_in[5] to constant 0 [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:32] +WARNING: [Synth 8-3295] tying undriven pin dut0:usermem_data_in[4] to constant 0 [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:32] +WARNING: [Synth 8-3295] tying undriven pin dut0:usermem_data_in[3] to constant 0 [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:32] +WARNING: [Synth 8-3295] tying undriven pin dut0:usermem_data_in[2] to constant 0 [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:32] +WARNING: [Synth 8-3295] tying undriven pin dut0:usermem_data_in[1] to constant 0 [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:32] +WARNING: [Synth 8-3295] tying undriven pin dut0:usermem_data_in[0] to constant 0 [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:32] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 427.793 ; gain = 131.727 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/hp/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc] +Finished Parsing XDC File [C:/Users/hp/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/hp/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/main_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/main_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 750.871 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 750.871 ; gain = 454.805 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 750.871 ; gain = 454.805 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 750.871 ; gain = 454.805 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6014] Unused sequential element mycounter_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v:122] +WARNING: [Synth 8-6014] Unused sequential element data_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v:7] +INFO: [Synth 8-5544] ROM "registerfile_reg[3]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "registerfile_reg[2]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "registerfile_reg[1]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "registerfile_reg[0]" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v:14] +INFO: [Synth 8-802] inferred FSM for state register 'stage_reg' in module 'control' +WARNING: [Synth 8-6014] Unused sequential element stage_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:42] +INFO: [Synth 8-5544] ROM "regfile_regwrite" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "regfile_regwrite" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "pc_jump" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "pc_jmpaddr" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "stage" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "stage" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "usermem_address" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "usermem_data_out" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "regfile_data" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "pc_jmpaddr" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "stage" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "stage" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5545] ROM "clk_out" won't be mapped to RAM because address size (33) is larger than maximum supported(25) +WARNING: [Synth 8-6014] Unused sequential element stage_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:42] +WARNING: [Synth 8-6014] Unused sequential element stage_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:42] +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE1 | 0000001 | 010 + iSTATE | 0000010 | 000 + iSTATE0 | 0000100 | 001 + iSTATE5 | 0001000 | 101 + iSTATE3 | 0010000 | 100 + iSTATE4 | 0100000 | 110 +* + iSTATE2 | 1000000 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'stage_reg' using encoding 'one-hot' in module 'control' +WARNING: [Synth 8-6014] Unused sequential element stage_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:42] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 750.871 ; gain = 454.805 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 33 Bit Adders := 1 + 2 Input 11 Bit Adders := 1 + 2 Input 8 Bit Adders := 3 + 3 Input 8 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 ++---XORs : + 2 Input 8 Bit XORs := 1 ++---Registers : + 33 Bit Registers := 1 + 11 Bit Registers := 1 + 8 Bit Registers := 15 + 4 Bit Registers := 2 + 2 Bit Registers := 1 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 33 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 16 + 4 Input 8 Bit Muxes := 3 + 8 Input 8 Bit Muxes := 2 + 6 Input 8 Bit Muxes := 3 + 3 Input 8 Bit Muxes := 2 + 21 Input 7 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 2 + 7 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 52 + 6 Input 1 Bit Muxes := 9 + 3 Input 1 Bit Muxes := 11 + 4 Input 1 Bit Muxes := 11 + 7 Input 1 Bit Muxes := 1 + 5 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module sram +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 8 +Module seven_seg +Detailed RTL Component Info : ++---Adders : + 2 Input 11 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 ++---Registers : + 11 Bit Registers := 1 + 4 Bit Registers := 2 + 2 Bit Registers := 1 ++---Muxes : + 4 Input 4 Bit Muxes := 2 +Module pc +Detailed RTL Component Info : ++---Adders : + 2 Input 8 Bit Adders := 1 ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module regfile +Detailed RTL Component Info : ++---Muxes : + 4 Input 8 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 4 +Module alu +Detailed RTL Component Info : ++---Adders : + 3 Input 8 Bit Adders := 1 ++---XORs : + 2 Input 8 Bit XORs := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 2 + 8 Input 8 Bit Muxes := 2 +Module control +Detailed RTL Component Info : ++---Adders : + 2 Input 8 Bit Adders := 2 ++---Registers : + 8 Bit Registers := 6 + 1 Bit Registers := 3 ++---Muxes : + 4 Input 8 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 11 + 6 Input 8 Bit Muxes := 3 + 3 Input 8 Bit Muxes := 2 + 21 Input 7 Bit Muxes := 1 + 7 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 47 + 6 Input 1 Bit Muxes := 9 + 3 Input 1 Bit Muxes := 11 + 4 Input 1 Bit Muxes := 11 + 7 Input 1 Bit Muxes := 1 + 5 Input 1 Bit Muxes := 3 +Module clkDiv +Detailed RTL Component Info : ++---Adders : + 2 Input 33 Bit Adders := 1 ++---Registers : + 33 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 33 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6014] Unused sequential element dut0/cntrl0/usermem_data_out_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:48] +WARNING: [Synth 8-6014] Unused sequential element dut0/cntrl0/usermem_address_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:48] +WARNING: [Synth 8-6014] Unused sequential element dut0/cntrl0/rw_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v:49] +INFO: [Synth 8-5545] ROM "clkDiv0/clk_out" won't be mapped to RAM because address size (33) is larger than maximum supported(25) +WARNING: [Synth 8-6014] Unused sequential element seven_seg0/mycounter_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v:122] +WARNING: [Synth 8-6014] Unused sequential element dut0/pc0/data_reg was removed. [C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v:7] +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][0]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][0]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][0]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][0]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][1]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][1]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][1]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][2]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][2]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][3]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][3]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][4]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][4]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][5]' (FD) to 'sram0/memory_array_reg[10][6]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][6]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][6]' (FD) to 'sram0/memory_array_reg[10][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[3][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[2][6]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[10][7]' (FD) to 'sram0/memory_array_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[9][7]' (FD) to 'sram0/memory_array_reg[8][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[8][7]' (FD) to 'sram0/memory_array_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[7][7]' (FD) to 'sram0/memory_array_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[6][7]' (FD) to 'sram0/memory_array_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'sram0/memory_array_reg[4][7]' (FD) to 'sram0/memory_array_reg[2][7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sram0/memory_array_reg[3][7] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\sram0/memory_array_reg[2][7] ) +WARNING: [Synth 8-3332] Sequential element (sram0/memory_array_reg[3][7]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (sram0/memory_array_reg[2][7]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/instruction_reg[5]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[7]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[6]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[5]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[4]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[3]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[2]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[1]) is unused and will be removed from module main. +WARNING: [Synth 8-3332] Sequential element (dut0/cntrl0/sp_reg[0]) is unused and will be removed from module main. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 750.871 ; gain = 454.805 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 751.156 ; gain = 455.090 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 751.453 ; gain = 455.387 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 2| +|2 |CARRY4 | 10| +|3 |LUT1 | 36| +|4 |LUT2 | 55| +|5 |LUT3 | 33| +|6 |LUT4 | 31| +|7 |LUT5 | 36| +|8 |LUT6 | 57| +|9 |FDRE | 119| +|10 |FDSE | 8| +|11 |IBUF | 3| +|12 |OBUF | 27| ++------+-------+------+ + +Report Instance Areas: ++------+-------------+----------+------+ +| |Instance |Module |Cells | ++------+-------------+----------+------+ +|1 |top | | 417| +|2 | clkDiv0 |clkDiv | 116| +|3 | dut0 |cpu | 221| +|4 | alu0 |alu | 2| +|5 | cntrl0 |control | 101| +|6 | pc0 |pc | 55| +|7 | reg0 |regfile | 63| +|8 | seven_seg0 |seven_seg | 48| ++------+-------------+----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 22 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 776.656 ; gain = 157.512 +Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 776.656 ; gain = 480.590 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +117 Infos, 153 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 776.656 ; gain = 483.043 +INFO: [Common 17-1381] The checkpoint 'C:/Users/hp/end_game/end_game.runs/synth_1/main.dcp' has been generated. +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 776.656 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sat Nov 23 00:05:44 2019... diff --git a/end_game/end_game.runs/synth_1/runme.sh b/end_game/end_game.runs/synth_1/runme.sh new file mode 100644 index 0000000..387b68e --- /dev/null +++ b/end_game/end_game.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/SDK/2017.1/bin;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2017.1/bin +else + PATH=C:/Xilinx/SDK/2017.1/bin;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2017.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/hp/end_game/end_game.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log main.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source main.tcl diff --git a/end_game/end_game.runs/synth_1/vivado.jou b/end_game/end_game.runs/synth_1/vivado.jou new file mode 100644 index 0000000..5be7625 --- /dev/null +++ b/end_game/end_game.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.1 (64-bit) +# SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017 +# IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 +# Start of session at: Sat Nov 23 00:05:11 2019 +# Process ID: 1084 +# Current directory: C:/Users/hp/end_game/end_game.runs/synth_1 +# Command line: vivado.exe -log main.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source main.tcl +# Log file: C:/Users/hp/end_game/end_game.runs/synth_1/main.vds +# Journal file: C:/Users/hp/end_game/end_game.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source main.tcl -notrace diff --git a/end_game/end_game.runs/synth_1/vivado.pb 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zPr23X4gz|51^7bO5~BXICE~znAc?rsbB%UjAJW{CAS8y==eZ!1h4EbzZWaWHT}Xah zj=o^pW_4vHFm00x$JXH5~|@(r0ZnmT~D6|iIk9;dW0XoZ5>eT^ko=UHWY6NyA`> literal 0 HcmV?d00001 diff --git a/end_game/end_game.sim/sim_1/behav/compile.bat b/end_game/end_game.sim/sim_1/behav/compile.bat new file mode 100644 index 0000000..9b6ad02 --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/compile.bat @@ -0,0 +1,11 @@ +@echo off +set xv_path=C:\\Xilinx\\Vivado\\2017.1\\bin +echo "xvlog -m64 --relax -prj main_simu_vlog.prj" +call %xv_path%/xvlog -m64 --relax -prj main_simu_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/end_game/end_game.sim/sim_1/behav/compile.log b/end_game/end_game.sim/sim_1/behav/compile.log new file mode 100644 index 0000000..7d38d7b --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/compile.log @@ -0,0 +1,30 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/clock_div.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module clkDiv +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module control +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module cpu +INFO: [VRFC 10-2458] undeclared symbol pc_jump, assumed default net type wire [C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v:10] +INFO: [VRFC 10-2458] undeclared symbol pc_freeze, assumed default net type wire [C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v:10] +INFO: [VRFC 10-2458] undeclared symbol regfile_regwrite, assumed default net type wire [C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v:12] +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module main +WARNING: [VRFC 10-1315] redeclaration of ansi port clk is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:24] +WARNING: [VRFC 10-1315] redeclaration of ansi port datamem_address is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:25] +WARNING: [VRFC 10-1315] redeclaration of ansi port value1 is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:27] +WARNING: [VRFC 10-1315] redeclaration of ansi port value2 is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:28] +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module pc +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/reg.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module regfile +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module seven_seg +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module sram +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sim_1/new/main_tb.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module main_simu +WARNING: [VRFC 10-965] invalid size of integer constant literal [C:/Users/hp/end_game/end_game.srcs/sim_1/new/main_tb.v:46] +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.sim/sim_1/behav/glbl.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module glbl diff --git a/end_game/end_game.sim/sim_1/behav/elaborate.bat b/end_game/end_game.sim/sim_1/behav/elaborate.bat new file mode 100644 index 0000000..20c5802 --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/elaborate.bat @@ -0,0 +1,9 @@ +@echo off +set xv_path=C:\\Xilinx\\Vivado\\2017.1\\bin +call %xv_path%/xelab -wto bbee60fc56e8409db2cdf5ab01427605 -m64 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot main_simu_behav xil_defaultlib.main_simu xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/end_game/end_game.sim/sim_1/behav/elaborate.log b/end_game/end_game.sim/sim_1/behav/elaborate.log new file mode 100644 index 0000000..c220bfb --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/elaborate.log @@ -0,0 +1,35 @@ +Vivado Simulator 2017.1 +Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2017.1/bin/unwrapped/win64.o/xelab.exe -wto bbee60fc56e8409db2cdf5ab01427605 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot main_simu_behav xil_defaultlib.main_simu xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v" Line 110. Module seven_seg doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v" Line 1. Module cpu doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v" Line 1. Module pc doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/reg.v" Line 2. Module regfile doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v" Line 1. Module alu doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v" Line 1. Module control doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/clock_div.v" Line 1. Module clkDiv doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v" Line 110. Module seven_seg doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v" Line 1. Module cpu doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v" Line 1. Module pc doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/reg.v" Line 2. Module regfile doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v" Line 1. Module alu doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v" Line 1. Module control doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "C:/Users/hp/end_game/end_game.srcs/sources_1/new/clock_div.v" Line 1. Module clkDiv doesn't have a timescale but at least one module in design has a timescale. +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module xil_defaultlib.sram +Compiling module xil_defaultlib.seven_seg +Compiling module xil_defaultlib.pc +Compiling module xil_defaultlib.regfile +Compiling module xil_defaultlib.alu +Compiling module xil_defaultlib.control +Compiling module xil_defaultlib.cpu +Compiling module xil_defaultlib.clkDiv +Compiling module xil_defaultlib.main +Compiling module xil_defaultlib.main_simu +Compiling module xil_defaultlib.glbl +Built simulation snapshot main_simu_behav diff --git a/end_game/end_game.sim/sim_1/behav/glbl.v b/end_game/end_game.sim/sim_1/behav/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/end_game/end_game.sim/sim_1/behav/main_simu.tcl b/end_game/end_game.sim/sim_1/behav/main_simu.tcl new file mode 100644 index 0000000..f09b1c3 --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/main_simu.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/end_game/end_game.sim/sim_1/behav/main_simu_behav.wdb b/end_game/end_game.sim/sim_1/behav/main_simu_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..9e8224847376116e814e25d811af3dffa03acd2c GIT binary patch literal 36357 zcmeI43s_Uf*09s|w6@2#czRK*MzmV5Ra8X8Xz-3!4OUdVVMIhk5Rj0BO9Jh&t+rOs zTD4vRZLLi!6;woS654u+H^iDMcTrI>T!Kh|5N`ikvuAsD_c8dL{@?ff=YPI4&$F1> zGw)urX3d(}v$K6%;veWA6yDEs%HkRQrcYToW$F}<8U03$7A#@vJ^VMw1HHq7Lj^QV zrg_KE0xv5Le@4HVv**IZ!^{f=tuVKLfxH-G7zmj5bzrcczmMQ~xWa_WkQgNx zEm$U4f>nY6AkhA`%*Q*>J5=fqrXUXJ2OS+9F?h=ekZypG`=5gx6E?6yD&S8$+~ETG zWB6HsF|t^YMj7D|CI$F|W$*||3urE<`L{HuLtn6P;cQyNWT+dHg%(iFswoK5BzOiG6vk5m0hma9gSTKcdyNDpF#U1D`%y3< zi{Xel6QEFl)CJ@Pke5J^eHR3EzX3wJg&YIp6_DYyu0Q0++S6;uNJ3jM;eBs|;C-l% z)dNLhFUw$PqP^oms0*O<4+iV74egr&VvCs!Z8#2$4_gd|{fi*dPMERKhJM)C3F8E9 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-L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "main_simu_behav" "xil_defaultlib.main_simu" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/TempBreakPointFile.txt b/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..8082a44 --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/_xsim_webtallk.info b/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/_xsim_webtallk.info new file mode 100644 index 0000000..7c07380 --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/_xsim_webtallk.info @@ -0,0 +1,5 @@ +1574447612 +1574448328 +3 +1 +bbee60fc56e8409db2cdf5ab01427605 diff --git a/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/usage_statistics_ext_xsim.html b/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..69f7bb7 --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version1846317
date_generatedSat Nov 23 00:15:28 2019os_platformWIN64
product_versionXSIM v2017.1 (64-bit)project_idbbee60fc56e8409db2cdf5ab01427605
project_iteration2random_ida20516f5-6568-4922-95cb-fd63966b3ff7
registration_id211458424_1777531420_210673176_760route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-6700 CPU @ 3.40GHzcpu_speed3408 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram17.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=2runtime=1 ussimulation_memory=6936_KBsimulation_time=0.03_sec
trace_waveform=true
+

+ + diff --git a/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/usage_statistics_ext_xsim.xml b/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..3e9168c --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/xsim.dir/main_simu_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
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b/end_game/end_game.sim/sim_1/behav/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,15 @@ +0.6 +2017.1 +Apr 14 2017 +19:10:27 +C:/Users/hp/end_game/end_game.sim/sim_1/behav/glbl.v,1492045073,verilog,,,,glbl,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sim_1/new/main_tb.v,1574444723,verilog,,,,main_simu,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v,1574447080,verilog,,,,alu,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/clock_div.v,1574443035,verilog,,,,clkDiv,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v,1574438486,verilog,,,,control,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v,1574444669,verilog,,,,cpu,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v,1574446989,verilog,,,,main,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v,1574438348,verilog,,,,pc,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/reg.v,1574445243,verilog,,,,regfile,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v,1574438702,verilog,,,,seven_seg,,,,,,,, +C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v,1574447589,verilog,,,,sram,,,,,,,, diff --git a/end_game/end_game.sim/sim_1/behav/xsim.dir/xsim.svtype b/end_game/end_game.sim/sim_1/behav/xsim.dir/xsim.svtype new file mode 100644 index 0000000000000000000000000000000000000000..5142c798fef8e9d0c125e588c5b73fa4ec2baab0 GIT binary patch literal 8 Kcmd;JfB*mhNB{`{ literal 0 HcmV?d00001 diff --git a/end_game/end_game.sim/sim_1/behav/xsim.ini b/end_game/end_game.sim/sim_1/behav/xsim.ini new file mode 100644 index 0000000..f9860a2 --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/end_game/end_game.sim/sim_1/behav/xvlog.log b/end_game/end_game.sim/sim_1/behav/xvlog.log new file mode 100644 index 0000000..7d38d7b --- /dev/null +++ b/end_game/end_game.sim/sim_1/behav/xvlog.log @@ -0,0 +1,30 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/alu.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module alu +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/clock_div.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module clkDiv +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/control.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module control +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module cpu +INFO: [VRFC 10-2458] undeclared symbol pc_jump, assumed default net type wire [C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v:10] +INFO: [VRFC 10-2458] undeclared symbol pc_freeze, assumed default net type wire [C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v:10] +INFO: [VRFC 10-2458] undeclared symbol regfile_regwrite, assumed default net type wire [C:/Users/hp/end_game/end_game.srcs/sources_1/new/cpu.v:12] +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module main +WARNING: [VRFC 10-1315] redeclaration of ansi port clk is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:24] +WARNING: [VRFC 10-1315] redeclaration of ansi port datamem_address is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:25] +WARNING: [VRFC 10-1315] redeclaration of ansi port value1 is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:27] +WARNING: [VRFC 10-1315] redeclaration of ansi port value2 is not allowed [C:/Users/hp/end_game/end_game.srcs/sources_1/new/main.v:28] +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/pc.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module pc +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/reg.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module regfile +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/seven_seg.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module seven_seg +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sources_1/new/sram.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module sram +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.srcs/sim_1/new/main_tb.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module main_simu +WARNING: [VRFC 10-965] invalid size of integer constant literal [C:/Users/hp/end_game/end_game.srcs/sim_1/new/main_tb.v:46] +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/hp/end_game/end_game.sim/sim_1/behav/glbl.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module glbl diff --git a/end_game/end_game.sim/sim_1/behav/xvlog.pb b/end_game/end_game.sim/sim_1/behav/xvlog.pb new file mode 100644 index 0000000000000000000000000000000000000000..0c0352cfbb911d72c464492c713842dbc3d9ca42 GIT binary patch literal 5379 zcmd5=TWi!n6mGWdE{;$Gf|iOfR4XF2X|k7I@Ig_*J5se`U&3rMyB#~3gqdV7{Q*Av zfBYxj5MTTiq9@z6v?kT0WZQk(VJFO)@0)YJ^Ua{o8oG8z5Z>QqqKy|6ZZS^r{DPXt zOoTq>tSO1?!;C&XH)XC>Yd6mJ6!SV%vKDi!OQ^C5L+-b&ic4E0;^F$Af%OPA?yeiJ z6qU-@4h$+>yG=a0KUh-IQHJs(=}={xhM--8@Mx)%verDB=`n5(W5BkO-)vRP<(rn( zsBTXL)4l2U+Js(0FVK0ikI(bn2;dFCOjb?vFqVsG5~8Q9TZVPv>x0XFA0=dom0-vGv`~>$%xj|V{>5Q=iIyl0($6oT&xI_HuQY@cTn*OgSMlfhcgh4pJ8 zSiu8zz(P{c<{WLL5as1!KKGfLC3v9prU zM+>DbpA8>&^K9IW-91pz4i&a4n87#M6AwJ${vNV%ICc(1N#YfnfcYFq96lR!<50QG z8@}Ac#>ozwg%X!9?*==7$El20!4Dd`&IB}U2KPX=OJn;6k6yG*C5F4W3W*5e0W74F zaPV%EYmL9GTgIDQlA)svTCH(pyNjPtU;_vJ*~d|Ky9cQDpKixI1Gt96Z_;hjG1|OY a?BhwkqKU(2E1DUE?h6-hP{)_9uKfl`g^hCn literal 0 HcmV?d00001 diff --git a/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc b/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc new file mode 100644 index 0000000..3b3bac4 --- /dev/null +++ b/end_game/end_game.srcs/constrs_1/new/my_constraint.xdc @@ -0,0 +1,72 @@ +# Clock signal +set_property PACKAGE_PIN W5 [get_ports clk] + set_property IOSTANDARD LVCMOS33 [get_ports clk] + + +#seven-segment LED display +set_property PACKAGE_PIN W7 [get_ports {data[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {data[6]}] +set_property PACKAGE_PIN W6 [get_ports {data[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {data[5]}] +set_property PACKAGE_PIN U8 [get_ports {data[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {data[4]}] +set_property PACKAGE_PIN V8 [get_ports {data[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {data[3]}] +set_property PACKAGE_PIN U5 [get_ports {data[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {data[2]}] +set_property PACKAGE_PIN V5 [get_ports {data[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {data[1]}] +set_property PACKAGE_PIN U7 [get_ports {data[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {data[0]}] + +set_property PACKAGE_PIN U2 [get_ports {anode[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode[0]}] +set_property PACKAGE_PIN U4 [get_ports {anode[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode[1]}] +set_property PACKAGE_PIN V4 [get_ports {anode[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode[2]}] +set_property PACKAGE_PIN W4 [get_ports {anode[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode[3]}] + +set_property PACKAGE_PIN U16 [get_ports {datamem_address[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {datamem_address[0]}] + set_property PACKAGE_PIN E19 [get_ports {datamem_address[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {datamem_address[1]}] + set_property PACKAGE_PIN U19 [get_ports {datamem_address[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {datamem_address[2]}] + set_property PACKAGE_PIN V19 [get_ports {datamem_address[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {datamem_address[3]}] + set_property PACKAGE_PIN W18 [get_ports {datamem_address[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {datamem_address[4]}] + set_property PACKAGE_PIN U15 [get_ports {datamem_address[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {datamem_address[5]}] + set_property PACKAGE_PIN U14 [get_ports {datamem_address[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {datamem_address[6]}] + set_property PACKAGE_PIN V14 [get_ports {datamem_address[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {datamem_address[7]}] + set_property PACKAGE_PIN V13 [get_ports {idata[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {idata[0]}] + set_property PACKAGE_PIN V3 [get_ports {idata[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {idata[1]}] + set_property PACKAGE_PIN W3 [get_ports {idata[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {idata[2]}] + set_property PACKAGE_PIN U3 [get_ports {idata[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {idata[3]}] + set_property PACKAGE_PIN P3 [get_ports {idata[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {idata[4]}] + set_property PACKAGE_PIN N3 [get_ports {idata[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {idata[5]}] + set_property PACKAGE_PIN P1 [get_ports {idata[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {idata[6]}] + set_property PACKAGE_PIN L1 [get_ports {idata[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {idata[7]}] + + +set_property PACKAGE_PIN T18 [get_ports interrupt] + set_property IOSTANDARD LVCMOS33 [get_ports interrupt] +#set_property PACKAGE_PIN W19 [get_ports btnL] + #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +#set_property PACKAGE_PIN T17 [get_ports btnR] + #set_property IOSTANDARD LVCMOS33 [get_ports btnR] +set_property PACKAGE_PIN V16 [get_ports reset] + set_property IOSTANDARD LVCMOS33 [get_ports reset] \ No newline at end of file diff --git a/end_game/end_game.srcs/sim_1/new/cpusim.v b/end_game/end_game.srcs/sim_1/new/cpusim.v new file mode 100644 index 0000000..a30c66e --- /dev/null +++ b/end_game/end_game.srcs/sim_1/new/cpusim.v @@ -0,0 +1,76 @@ +module programmem(input [7:0] pgmaddr, output [7:0] pgmdata); + reg [7:0] pmemory[255:0]; + assign pgmdata=pmemory[pgmaddr]; + + initial + begin + pmemory[0]=8'h80; + pmemory[1]=8'h04; + pmemory[2]=8'h81; + pmemory[3]=8'h02; + pmemory[4]=8'h41; +// pmemory[5]=8'h00; +// pmemory[6]=8'hb2; +// pmemory[7]=8'h93; +// pmemory[8]=8'ha1; +// pmemory[9]=8'h00; + end +endmodule + +// Simple user memory for simulation +module usermem(input clk, input [7:0] uaddr, input [7:0] udata_i,output [7:0] udata_o, input rw); + reg [7:0] umemory[255:0]; + assign udata_o=rw?8'bZ:umemory[uaddr]; + always @(negedge clk) begin + if (rw==1) umemory[uaddr] <= udata_i; + end + initial + begin + umemory[0]<=8'h00; + umemory[1]<=8'h00; + umemory[2]<=8'h00; + umemory[255]<=8'hde; + end +endmodule + +module cpu_tb; + reg clk, reset, interrupt; + wire [7:0] datamem_data, usermem_data_in, usermem_data_out, datamem_address, usermem_address, idata,v1,v2; + wire rw; + programmem pgm(datamem_address,idata); + usermem umem(clk, usermem_address,usermem_data_out, usermem_data_in,rw); +cpu dut0 ( + .clk(clk), + .reset(reset), + .interrupt(interrupt), + .datamem_data(idata), + .usermem_data_in(usermem_data_in), + .datamem_address(datamem_address), + .usermem_address(usermem_address), + .usermem_data_out(usermem_data_out), + .rw(rw),.v1(v1),.v2(v2) + ); initial + begin + //$display("NopCPU testbench. All waveforms will be dumped to the dump.vcd file."); + //$dumpfile("waves.vcd"); + //$dumpvars(0, dut0); + //$monitor("Clock: %b Reset: %b \nAddress (Datamem): %h Address: (Usermem): %h)\n Data (Datamem): %h Data (Usermem): %h R/W: %b\n Time: %d\n",clk,reset,datamem_address,usermem_address,datamem_data,usermem_data_out,rw,$time); + clk = 1'b0; + reset = 1'b1; + interrupt = 1'b0; + @(posedge clk); + @(posedge clk); + reset = 1'b0; + end + always begin + forever begin + #1 clk = !clk; + end + end + /* Comment this out to test interrupts: */ + /*always + begin + #25 interrupt = ~interrupt; + #2 interrupt = ~interrupt; + end*/ +endmodule //cpu_tb \ No newline at end of file diff --git a/end_game/end_game.srcs/sim_1/new/main_tb.v b/end_game/end_game.srcs/sim_1/new/main_tb.v new file mode 100644 index 0000000..ba7ff13 --- /dev/null +++ b/end_game/end_game.srcs/sim_1/new/main_tb.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19.11.2019 22:13:10 +// Design Name: +// Module Name: main_simu +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module main_simu;//(input clk,input reset,input interrupt, output [7:0] idata ); +reg clk; +reg reset; +reg interrupt; +wire [7:0] idata; +wire [7:0] odata; +wire [3:0]anode; +wire [6:0]data; +wire [7:0] value1; +wire [7:0] value2; +main main0(clk,reset,interrupt,idata,odata,anode,data,value1,value2); + initial + begin + + //$monitor("Clock: %b Reset: %b \nAddress (Datamem): %h Address: (Usermem): %h)\n Data (Datamem): %h Data (Usermem): %h R/W: %b\n Time: %d\n",clk,reset,datamem_address,usermem_address,datamem_data,usermem_data,rw,$time); + clk = 1'b0; + reset = 1'b1; + interrupt = 1'b0; + repeat(4) #10 clk = !clk; + reset = 1'b0; + #1; + reset = 1'b1; + #1; + reset = 0'b0; + #1; + end + always + #1 clk = !clk; +endmodule diff --git a/end_game/end_game.srcs/sources_1/new/alu.v b/end_game/end_game.srcs/sources_1/new/alu.v new file mode 100644 index 0000000..b8c739e --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/alu.v @@ -0,0 +1,26 @@ +module alu (input [7:0] b,a, + input [3:0] opcode, + output reg [7:0] y); + reg [7:0] o, an, n, x, add, sub, rsn; + /* Decode the instruction */ + always @* begin + o <= a | b; + an <= a & b; + n <= ~a; + x <= a ^ b; + add <= a + b; + sub <= a - b; + rsn <= a >> b; + case (opcode) + 4'h0 /* OR */: y <= o; + 4'h1 /* AND */: y <= an; + 4'h2 /* NOT */: y <= n; + 4'h3 /* XOR */: y <= x; + 4'h4 /* ADD */: y <= add; + 4'h5 /* SUB */: y <= sub; + 4'h6 /* TX */: y <= b; + 4'h7 /* RSHIFTN */: y <= rsn; + default: y <= 8'bZ; + endcase + end +endmodule //alu \ No newline at end of file diff --git a/end_game/end_game.srcs/sources_1/new/clock_div.v b/end_game/end_game.srcs/sources_1/new/clock_div.v new file mode 100644 index 0000000..5540396 --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/clock_div.v @@ -0,0 +1,17 @@ +module clkDiv(input clk_in,input reset, output reg clk_out,output reg [7:0] value1, output reg [7:0] value2); + +reg [32:0] count; +//reg clk_out; +always @(posedge clk_in) begin + if(reset==1)begin + count <= 0; + end else begin + count <= count + 1; + if(count == 300000000) + begin + count<=0; + clk_out <= !clk_out; + end + end +end +endmodule \ No newline at end of file diff --git a/end_game/end_game.srcs/sources_1/new/control.v b/end_game/end_game.srcs/sources_1/new/control.v new file mode 100644 index 0000000..097143b --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/control.v @@ -0,0 +1,213 @@ +module control (input clk, reset, interrupt, + input [7:0] datamem_data, datamem_address, regfile_out1, + input [7:0] regfile_out2, alu_out, usermem_data_in, + output reg [3:0] alu_opcode, + output reg [7:0] regfile_data,usermem_data_out, + output reg [1:0] regfile_read1, regfile_read2, regfile_writereg, + output reg [7:0] usermem_address, pc_jmpaddr, + output reg rw, regfile_regwrite, pc_jump, pc_freeze); + /* Parameters */ + parameter state0 = 3'h0; + parameter state1 = 3'h1; + parameter state2 = 3'h2; + parameter state3 = 3'h3; + parameter state4 = 3'h4; + parameter state5 = 3'h5; + parameter state6 = 3'h6; + /* Flags */ + reg [2:0] stage; + reg [7:0] instruction_c; + reg [7:0] instruction; + reg [7:0] sp; + reg is_onecyc, is_alu; + reg eq; + /* Combinational logic goes here */ + always @(*) begin + instruction_c <= datamem_data; + is_alu <= (instruction_c[7:4] <= 4'h7); + is_onecyc <= (instruction_c[7:4] <= 4'hd); + alu_opcode <= instruction_c[7:4]; + regfile_read1 <= (stage == state0) ? instruction_c[3:2] : instruction[3:2]; + regfile_read2 <= (stage == state0) ? instruction_c[1:0] : instruction[1:0]; + regfile_writereg <= instruction[1:0]; + eq <= (regfile_out1 == regfile_out2); + pc_freeze <= (stage >= state4) ? 1 : 0; + end + always @(posedge clk) begin + regfile_regwrite = 0; + if(interrupt == 1) + begin + pc_jump <= 1; + pc_jmpaddr <= 8'hfd; + stage <= state2; + end + /* Check for reset*/ + else if(reset == 1) + begin + sp <= 0; + {instruction, regfile_data, usermem_data_out, usermem_address} <= 8'b0; + {rw, regfile_regwrite} <= 1'b0; + pc_jump <= 1; + pc_jmpaddr <= 8'b0; + stage <= state2; + end + /* Stage 1: Fetch instruction, execute it in case it does not require an operand: */ + else if (stage == state0) + begin + rw <= 0; + instruction <= datamem_data; + if (is_alu) + begin + rw <= 0; + regfile_regwrite <= 1; + regfile_data <= alu_out; + stage <= state0; + end + else if (is_alu == 0) begin + case (instruction_c[7:4]) + 4'h9 /* JMP/NOP */: + begin + pc_jmpaddr <= regfile_out2; + regfile_regwrite <= 0; + pc_jump <= 1; + stage <= state2; + end + 4'ha /* CALL */: + begin + rw <= 1; + sp <= sp + 1; + usermem_address <= sp; + usermem_data_out <= datamem_address; + pc_jmpaddr <= regfile_out2; + regfile_regwrite <= 0; + pc_jump <= 1; + stage <= state2; + end + 4'hb /* RTS */: + begin + if(instruction_c[3:0] == 4'h0) begin + pc_jump <= 1; + sp <= sp - 1; + usermem_address <= sp; + regfile_regwrite <= 0; + stage <= state4; + end + else if(instruction_c[3:0] == 4'h1) begin + /* STSP (b)*/ + regfile_regwrite <= 1; + regfile_data <= sp; + stage <= state0; + end + else if(instruction_c[3:0] == 4'h2) begin + /* POP (c) */ + sp <= sp - 1; + usermem_address <= sp; + regfile_regwrite <= 1; + regfile_regwrite <= 0; + stage <= state6; + end + else if(instruction_c[3:0] == 4'h4) begin + /* LDSP (b) */ + regfile_regwrite <= 0; + sp <= regfile_out1; + stage <= state0; + end + else if(instruction_c[3:0] == 4'h8) begin + /* PUSH (c) */ + rw <= 1; + sp <= sp + 1; + usermem_address <= sp + 1; + usermem_data_out <= regfile_out1; + stage <= state0; + end + end + 4'hc /* IEQ */: + begin + regfile_regwrite <= 0; + if(eq) + begin + stage <= state3; + end + else + stage <= state0; + end + 4'hd /* INE */: + begin + regfile_regwrite <= 0; + if(eq == 0) + begin + stage <= state3; + end + else + stage <= state0; + end + default: stage <= state1; + endcase + end + end + /* Stage 2: Fetch the operand and execute the relevant instruction: */ + else if (stage == state1) + begin + case (instruction[7:4]) + 4'h8 /* LD */: + begin + rw <= 0; + regfile_regwrite <= 1; + regfile_data <= datamem_data; + stage <= state0; + end + 4'he /* ST */: + begin + rw <= 1; + regfile_regwrite <= 0; + usermem_address <= datamem_data; + usermem_data_out <= regfile_out1; + stage <= state0; + end + 4'hf /* LDUMEM */: + begin + rw <= 0; + usermem_address <= datamem_data; + regfile_regwrite <= 1; + stage <= state5; + end + endcase + end + else if(stage == state2) + begin + rw <= 0; + instruction <= datamem_data; + pc_jump <= 0; + stage <= state0; + end + else if(stage == state3) + begin + /* Skip an instruction */ + if(is_onecyc) + stage <= state0; + else + stage <= state2; + end + else if(stage == state4) + begin + /* Execute RTS */ + rw <= 0; + pc_jmpaddr <= usermem_data_in; + stage <= state2; + end + else if(stage == state5) + begin + /* LDUMEM */ + instruction <= datamem_data; + regfile_data <= usermem_data_in; + stage <= state0; + end + else if(stage == state6) + begin + /* POP (c) */ + instruction <= datamem_data; + regfile_data <= usermem_data_in; + stage <= state0; + end + end +endmodule //control \ No newline at end of file diff --git a/end_game/end_game.srcs/sources_1/new/cpu.v b/end_game/end_game.srcs/sources_1/new/cpu.v new file mode 100644 index 0000000..f4762e2 --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/cpu.v @@ -0,0 +1,21 @@ +module cpu(input /*clr,*/clk, reset, interrupt, + input [7:0] datamem_data, usermem_data_in, + output [7:0] datamem_address, usermem_address, usermem_data_out, + output rw,[7:0]v1,[7:0]v2); + wire [1:0] regfile_read1, regfile_read2, regfile_writereg; + wire [7:0] pc_jumpaddr, regfile_data, regfile_out1, regfile_out2; + wire [7:0] alu_out; + wire [3:0] alu_opcode; + + pc pc0(clk, reset, pc_jump, pc_freeze, pc_jumpaddr, datamem_address); + regfile reg0(regfile_read1, regfile_read2, regfile_writereg, + regfile_data,/*clr,*/ clk, regfile_regwrite, + regfile_out1, regfile_out2,v1,v2); + alu alu0(regfile_out1, regfile_out2, alu_opcode, alu_out); + control cntrl0(clk, reset, interrupt, datamem_data, datamem_address, regfile_out1, regfile_out2, + alu_out, usermem_data_in, alu_opcode, + regfile_data, usermem_data_out, regfile_read1, regfile_read2, + regfile_writereg, usermem_address, + pc_jumpaddr, rw, regfile_regwrite, + pc_jump, pc_freeze); +endmodule //cpu \ No newline at end of file diff --git a/end_game/end_game.srcs/sources_1/new/main.v b/end_game/end_game.srcs/sources_1/new/main.v new file mode 100644 index 0000000..8c69df1 --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/main.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19.11.2019 22:07:40 +// Design Name: +// Module Name: main +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module main(input clk,input reset,input interrupt, output [7:0] idata, output [7:0] datamem_address, [3:0]anode, [6:0]data/*output [7:0] value1, output [7:0] value2*/); + wire clk,clk_out, reset, interrupt; + wire [7:0] datamem_data, usermem_data_in,usermem_data_out, datamem_address, usermem_address, idata; + wire rw; + wire [7:0] value1; + wire [7:0]value2; +// reg clr; + sram sram0(reset, datamem_address,idata); + seven_seg seven_seg0(clk,value2,value1,anode,data); + cpu dut0(/*clr,*/clk_out, reset, interrupt, idata, usermem_data_in, + datamem_address, usermem_address,usermem_data_out, rw, value1,value2 + ); +// always@(posedge reset) begin +// if(reset == 1) begin +// clr = 1; +// idata = 0; +// end +// else begin +// clr = 0; +// end +// end + clkDiv clkDiv0(clk,reset,clk_out); + +endmodule diff --git a/end_game/end_game.srcs/sources_1/new/pc.v b/end_game/end_game.srcs/sources_1/new/pc.v new file mode 100644 index 0000000..23f03cc --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/pc.v @@ -0,0 +1,16 @@ +module pc(input clk, reset, jump, freeze, + input [7:0] jmpaddr, + output reg[7:0] data); + + always @(posedge clk) begin + if (reset == 1) + data <= 8'b0; + else if (reset == 0) + begin + if (jump == 1) + data <= jmpaddr; + else + data <= freeze? data : data + 1; + end + end +endmodule //pc \ No newline at end of file diff --git a/end_game/end_game.srcs/sources_1/new/reg.v b/end_game/end_game.srcs/sources_1/new/reg.v new file mode 100644 index 0000000..d77ffdc --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/reg.v @@ -0,0 +1,30 @@ + +module regfile (input [1:0] readreg1, readreg2, writereg, + input [7:0] data,/*clr,*/ + input clk, regwrite, + output [7:0] read1, read2,v1,v2); + reg [7:0] registerfile [3:0]; + initial begin + registerfile[2'd0] <= 8'b0; + registerfile[2'd1] <= 8'b0; + registerfile[2'd2] <= 8'b0; + registerfile[2'd3] <= 8'b0; + end + always @(negedge clk) begin + if(regwrite == 1) + registerfile[writereg] <= data; +// else if(clr == 1) +// begin +// registerfile[2'd0] <= 8'b0; +// registerfile[2'd1] <= 8'b0; +// registerfile[2'd2] <= 8'b0; +// registerfile[2'd3] <= 8'b0; +// end + + end + + assign read1 = (regwrite && readreg1 == writereg)? data: registerfile[readreg1]; + assign read2 = (regwrite && readreg2 == writereg)? data: registerfile[readreg2]; + assign v1 = registerfile[0]; + assign v2 = registerfile[1]; +endmodule //regfile \ No newline at end of file diff --git a/end_game/end_game.srcs/sources_1/new/seven_seg.v b/end_game/end_game.srcs/sources_1/new/seven_seg.v new file mode 100644 index 0000000..b722a5a --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/seven_seg.v @@ -0,0 +1,243 @@ +//module mode10( +//input clk, +//input reset, +//input [15:0]x, +//output [6:0]data, +//output [3:0] cathod +//); +//reg [3:0]counter; +//reg [1:0] count; +//always @(negedge clk or negedge reset) +// begin +// if (reset ==0) +// begin +// count = 3; +// end + +// else begin +// counter = x[(count*3)+3:count*4]; +// count=count+1; +// end + +//always @ (counter) begin +// case (counter) +// 4'b0000 : //Hexadecimal 0 +// data = 7'b1111110; +// 4'b0001 : //Hexadecimal 1 +// data = 7'b0110000 ; +// 4'b0010 : // Hexadecimal 2 +// data = 7'b1101101 ; +// 4'b0011 : // Hexadecimal 3 +// data = 7'b1111001 ; +// 4'b0100 : // Hexadecimal 4 +// data = 7'b0110011 ; +// 4'b0101 : // Hexadecimal 5 +// data = 7'b1011011 ; +// 4'b0110 : // Hexadecimal 6 +// data = 7'b1011111 ; +// 4'b0111 : // Hexadecimal 7 +// data = 7'b1110000; +// 4'b1000 : //Hexadecimal 8 +// data = 7'b1111111; +// 4'b1001 : //Hexadecimal 9 +// data = 7'b1111011 ; +// 4'b1010 : // Hexadecimal A +// data = 7'b1110111 ; +// 4'b1011 : // Hexadecimal B +// data = 7'b0011111; +// 4'b1100 : // Hexadecimal C +// data = 7'b1001110 ; +// 4'b1101 : // Hexadecimal D +// data = 7'b0111101 ; +// 4'b1110 : // Hexadecimal E +// data = 7'b1001111 ; +// 4'b1111 : // Hexadecimal F +// data = 7'b1000111 ; +// endcase +//end + +//always @(count) begin +// case (count) +// 4'b00: cathod=4'b0000; +// 4'b00: cathod=4'b0000; + +//endmodule + + +//module hex_to_7segment( +// in ,select, data +// ); + +//input [3:0] in; // Input from DIP Switches +//output select; +//output [6:0] data; + +//parameter A = 7'b0000001; +//parameter B = 7'b0000010; +//parameter C = 7'b0000100; +//parameter D = 7'b0001000; +//parameter E = 7'b0010000; +//parameter F = 7'b0100000; +//parameter G = 7'b1000000; + + +//assign select = 1'b1; // Which of the the 3 seven segments we wish to display + +//assign data = +// (in == 4'h0) ? A|B|C|D|E|F : // Display 0 +// (in == 4'h1) ? B|C : // Display 1 +// (in == 4'h2) ? A|B|G|E|D : // Display 2 +// (in == 4'h3) ? A|B|C|D|G : // Display 3 +// (in == 4'h4) ? F|B|G|C : // Display 4 +// (in == 4'h5) ? A|F|G|C|D : // Display 5 +// (in == 4'h6) ? A|F|G|C|D|E : // Display 6 +// (in == 4'h7) ? A|B|C : // Display 7 +// (in == 4'h8) ? A|B|C|D|E|F|G : // Display 8 +// (in == 4'h9) ? A|B|C|D|F|G : // Display 9 +// (in == 4'ha) ? A|F|B|G|E|C : // Display A +// (in == 4'hb) ? F|G|C|D|E : // Display B +// (in == 4'hc) ? G|E|D : // Display C +// (in == 4'hd) ? B|C|G|E|D : // Display D +// (in == 4'he) ? A|F|G|E|D : // Display E +// (in == 4'hf) ? A|F|G|E : // Display F +// 4'bz; + +//endmodule + + +// fpga4student.com: FPGA projects, Verilog projects, VHDL projects +// FPGA tutorial: seven-segment LED display controller on Basys 3 FPGA +module seven_seg( + input clock_100Mhz, // 100 Mhz clock source on Basys 3 FPGA + input [7:0]b, + input [7:0]a, + output reg [3:0] Anode_Activate, // anode signals of the 7-segment LED display + output reg [6:0] LED_out// cathode patterns of the 7-segment LED display + ); +// + reg [3:0] LED_BCD; + reg [1:0]count = 0; + reg [10:0] mycounter = 0; + always@(posedge clock_100Mhz) begin + if(mycounter==0) begin + if(count==0) begin + LED_BCD = a[7:4]; + Anode_Activate = 4'b0111; + end + else if(count==1) begin + LED_BCD = a[3:0]; + Anode_Activate = 4'b1011; + end + else if(count==2) begin + LED_BCD = b[7:4]; + Anode_Activate = 4'b1101; + end + else begin + LED_BCD = b[3:0]; + Anode_Activate = 4'b1110; + end + + count = count + 1; + end + mycounter = mycounter + 1; + end + + // Cathode patterns of the 7-segment LED display + always @(*) + begin + case(LED_BCD) + 4'b0000: LED_out = 7'b0000001; // "0" + 4'b0001: LED_out = 7'b1001111; // "1" + 4'b0010: LED_out = 7'b0010010; // "2" + 4'b0011: LED_out = 7'b0000110; // "3" + 4'b0100: LED_out = 7'b1001100; // "4" + 4'b0101: LED_out = 7'b0100100; // "5" + 4'b0110: LED_out = 7'b0100000; // "6" + 4'b0111: LED_out = 7'b0001111; // "7" + 4'b1000: LED_out = 7'b0000000; // "8" + 4'b1001: LED_out = 7'b0000100; // "9" + 4'b1010: LED_out = 7'b0001000; // "A" + 4'b1011: LED_out = 7'b1100000; // "b" + 4'b1100: LED_out = 7'b0110001; // "C" + 4'b1101: LED_out = 7'b1000010; // "d" + 4'b1110: LED_out = 7'b0110000; // "E" + default: LED_out = 7'b0111000; // "F" + endcase + end + endmodule + + + + +// reg [26:0] one_second_counter; // counter for generating 1 second clock enable + // wire one_second_enable;// one second enable for counting numbers + // reg [15:0] displayed_number; // counting number to be displayed + // reg [19:0] refresh_counter; // 20-bit for creating 10.5ms refresh period or 380Hz refresh rate + // // the first 2 MSB bits for creating 4 LED-activating signals with 2.6ms digit period + // wire [1:0] LED_activating_counter; + // // count 0 -> 1 -> 2 -> 3 + // // activates LED1 LED2 LED3 LED4 + // // and repeat + + + + + +// always @(posedge clock_100Mhz or posedge reset) +// begin +// if(reset==1) +// one_second_counter <= 0; +// else begin +// if(one_second_counter>=99999999) +// one_second_counter <= 0; +// else +// one_second_counter <= one_second_counter + 1; +// end +// end +// assign one_second_enable = (one_second_counter==99999999)?1:0; +// always @(posedge clock_100Mhz or posedge reset) +// begin +// if(reset==1) +// displayed_number <= 0; +// else if(one_second_enable==1) +// displayed_number <= displayed_number + 1; +// end +// always @(posedge clock_100Mhz or posedge reset) +// begin +// if(reset==1) +// refresh_counter <= 0; +// else +// refresh_counter <= refresh_counter + 1; +// end +// assign LED_activating_counter = refresh_counter[19:18]; +// // anode activating signals for 4 LEDs, digit period of 2.6ms +// // decoder to generate anode signals +// always @(*) +// begin +// case(LED_activating_counter) +// 2'b00: begin +// Anode_Activate = 4'b0111; +// // activate LED1 and Deactivate LED2, LED3, LED4 +// LED_BCD = displayed_number/1000; +// // the first digit of the 16-bit number +// end +// 2'b01: begin +// Anode_Activate = 4'b1011; +// // activate LED2 and Deactivate LED1, LED3, LED4 +// LED_BCD = (displayed_number % 1000)/100; +// // the second digit of the 16-bit number +// end +// 2'b10: begin +// Anode_Activate = 4'b1101; +// // activate LED3 and Deactivate LED2, LED1, LED4 +// LED_BCD = ((displayed_number % 1000)%100)/10; +// // the third digit of the 16-bit number +// end +// 2'b11: begin +// Anode_Activate = 4'b1110; +// // activate LED4 and Deactivate LED2, LED3, LED1 +// LED_BCD = ((displayed_number % 1000)%100)%10; +// // the fourth digit of the 16-bit number +// end +// endcase +// end \ No newline at end of file diff --git a/end_game/end_game.srcs/sources_1/new/sram.v b/end_game/end_game.srcs/sources_1/new/sram.v new file mode 100644 index 0000000..5b23f41 --- /dev/null +++ b/end_game/end_game.srcs/sources_1/new/sram.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19.11.2019 20:12:38 +// Design Name: +// Module Name: sram +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sram( + input wire reset, + input wire [7:0] mem_address, + output [7:0] o_data + ); + + reg [7:0] memory_array [0:255]; + always @(posedge reset) + begin + memory_array[2] = 8'h80; + memory_array[3] = 8'h01; + memory_array[4] = 8'h81; + memory_array[5] = 8'h01; + memory_array[6] = 8'h82; + memory_array[7] = 8'h08; + memory_array[8] = 8'h41; + memory_array[9] = 8'h44; + memory_array[10] = 8'h92; +// memory_array[11] = 8'h41; +// memory_array[12] = 8'h61; +// memory_array[13] = 8'h71; +// memory_array[14] = 8'h90; +// memory_array[15] = 8'h; +// memory_array[99] = 8'hc1; +// memory_array[100] = 8'hc7; +// memory_array[101] = 8'h41; +// memory_array[102] = 8'h51; +// memory_array[103] = 8'h61; + + end + + assign o_data = memory_array[mem_address]; + +endmodule \ No newline at end of file diff --git a/end_game/end_game.xpr b/end_game/end_game.xpr new file mode 100644 index 0000000..e671c30 --- /dev/null +++ b/end_game/end_game.xpr @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +