From 8b1f8cdfd8119db12c664338edd894d9c46b7985 Mon Sep 17 00:00:00 2001 From: snkYmkrct Date: Fri, 17 Jan 2025 23:34:56 +0100 Subject: [PATCH] fix formatting --- ports/stm/peripherals/periph.h | 2 +- ports/stm/peripherals/pins.h | 2 +- .../peripherals/stm32h7/stm32h743xx/clocks.h | 2 +- .../peripherals/stm32h7/stm32h750xx/clocks.h | 2 +- .../peripherals/stm32h7/stm32h750xx/gpio.c | 24 +++++++++---------- .../peripherals/stm32h7/stm32h750xx/periph.h | 1 - 6 files changed, 16 insertions(+), 17 deletions(-) diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index b731ad1be9f7..e1a922cebc9d 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -136,4 +136,4 @@ typedef struct { #define HAS_TRNG 1 #define HAS_BASIC_TIM 1 #include "stm32h7/stm32h750xx/periph.h" -#endif \ No newline at end of file +#endif diff --git a/ports/stm/peripherals/pins.h b/ports/stm/peripherals/pins.h index ba5f83ad6ef1..7720ce0a1e0e 100644 --- a/ports/stm/peripherals/pins.h +++ b/ports/stm/peripherals/pins.h @@ -95,4 +95,4 @@ extern const mp_obj_type_t mcu_pin_type; #ifdef STM32H750xx #include "stm32h7/stm32h750xx/pins.h" -#endif \ No newline at end of file +#endif diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h index d6977e99c161..d59e51686de3 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.h @@ -69,4 +69,4 @@ #endif #ifndef BOARD_PLL_SOURCE #define BOARD_PLL_SOURCE (RCC_PLLSOURCE_HSE) -#endif \ No newline at end of file +#endif diff --git a/ports/stm/peripherals/stm32h7/stm32h750xx/clocks.h b/ports/stm/peripherals/stm32h7/stm32h750xx/clocks.h index 88d6bff62db8..958bdbe2b3cf 100644 --- a/ports/stm/peripherals/stm32h7/stm32h750xx/clocks.h +++ b/ports/stm/peripherals/stm32h7/stm32h750xx/clocks.h @@ -88,4 +88,4 @@ #endif #ifndef BOARD_PLL_SOURCE #define BOARD_PLL_SOURCE (RCC_PLLSOURCE_HSE) -#endif \ No newline at end of file +#endif diff --git a/ports/stm/peripherals/stm32h7/stm32h750xx/gpio.c b/ports/stm/peripherals/stm32h7/stm32h750xx/gpio.c index 3f9c887368e0..037e851de1fe 100644 --- a/ports/stm/peripherals/stm32h7/stm32h750xx/gpio.c +++ b/ports/stm/peripherals/stm32h7/stm32h750xx/gpio.c @@ -37,19 +37,19 @@ void stm32_peripherals_gpio_init(void) { __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); // Never reset pins - never_reset_pin_number(7, 0); // PH00 OSC32_IN - never_reset_pin_number(7, 1); // PH01 OSC32_OUT - never_reset_pin_number(0, 13); // PA13 SWDIO - never_reset_pin_number(0, 14); // PA14 SWCLK - // qspi flash pins for the Daisy Seed -- TODO ? - never_reset_pin_number(5, 6); // PF06 QSPI IO3 - never_reset_pin_number(5, 7); // PF07 QSPI IO2 - never_reset_pin_number(5, 8); // PF08 QSPI IO0 - never_reset_pin_number(5, 9); // PF09 QSPI IO1 - never_reset_pin_number(5, 10); // PF10 QSPI CLK - never_reset_pin_number(6, 6); // PG06 QSPI NCS + never_reset_pin_number(7, 0); // PH00 OSC32_IN + never_reset_pin_number(7, 1); // PH01 OSC32_OUT + never_reset_pin_number(0, 13); // PA13 SWDIO + never_reset_pin_number(0, 14); // PA14 SWCLK + // qspi flash pins for the Daisy Seed -- TODO ? + never_reset_pin_number(5, 6); // PF06 QSPI IO3 + never_reset_pin_number(5, 7); // PF07 QSPI IO2 + never_reset_pin_number(5, 8); // PF08 QSPI IO0 + never_reset_pin_number(5, 9); // PF09 QSPI IO1 + never_reset_pin_number(5, 10); // PF10 QSPI CLK + never_reset_pin_number(6, 6); // PG06 QSPI NCS } diff --git a/ports/stm/peripherals/stm32h7/stm32h750xx/periph.h b/ports/stm/peripherals/stm32h7/stm32h750xx/periph.h index 2b1261a7ef70..f4b8d6fe8c96 100644 --- a/ports/stm/peripherals/stm32h7/stm32h750xx/periph.h +++ b/ports/stm/peripherals/stm32h7/stm32h750xx/periph.h @@ -50,4 +50,3 @@ extern const mcu_periph_obj_t mcu_uart_rx_list[26]; #define TIM_BANK_ARRAY_LEN 14 #define TIM_PIN_ARRAY_LEN 58 extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; -