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When executing a Library.module(), when a Verilog module has non-lower-case name an error occurs.
This is due to the fact that both Library.entity() (VHDL) and Library.module() (Verilog) generate call to Library.test_bench(), that makes the name always lower-case.
Above calls trying to parameterize any non-lower-case Verilog module to fail.
The text was updated successfully, but these errors were encountered:
When executing a Library.module(), when a Verilog module has non-lower-case name an error occurs.
This is due to the fact that both Library.entity() (VHDL) and Library.module() (Verilog) generate call to Library.test_bench(), that makes the name always lower-case.
Above calls trying to parameterize any non-lower-case Verilog module to fail.
The text was updated successfully, but these errors were encountered: