Xoodyak-384-DOM1-v1.toml

name = "Xoodyak-384-DOM1-v1"
description = "Xoodyak with 1st order masking"
author = ["Richard Haeussler", "Abubakr Abdulgadir"]
url = "https://github.com/GMUCERG/Xoodyak-SCA"
license = "GPL-3.0"
version = "0.2.0"

dependencies = [
    { uri = "git+https://github.com/GMUCERG/LWC.git#hardware/LWC_SCA_wrapper.toml", rtl.pos = -1 },
]

[rtl]
sources = [
    "src_rtl/LWC_config.vhd",
    "src_rtl/LWC_rtl/NIST_LWAPI_pkg.vhd",
    "src_rtl/design_pkg.vhd",
    "src_rtl/xoodyak_constants.vhd",
    "src_rtl/lambda.vhd",
    "src_rtl/and_dom_n.vhd",
    "src_rtl/chi384.vhd",
    "src_rtl/rho_east.vhd",
    "src_rtl/xoodoo_round_pr.vhd",
    "src_rtl/cyclist_ops.vhd",
    "src_rtl/xoodyak_dp.vhd",
    "src_rtl/xoodyak_ctrl.vhd",
    "src_rtl/tag_verif.vhd",
    "src_rtl/CryptoCore.vhd",
    "src_rtl/LWC_rtl/FIFO.vhd",
    "src_rtl/LWC_rtl/PISO.vhd",
    "src_rtl/LWC_rtl/SIPO.vhd",
    "src_rtl/LWC_rtl/PreProcessor.vhd",
    "src_rtl/LWC_rtl/PostProcessor.vhd",
    "src_rtl/LWC_rtl/LWC_SCA.vhd",
]
# top = "LWC_SCA"
top = "LWC_SCA_wrapper"
clock.port = "clk"


[language]
vhdl.version = "2008"

[tb]
sources = ["src_tb/LWC_TB_SCA.vhd"]
top = "LWC_TB"

[tb.parameters]
G_FNAME_PDI = { file = "KAT/Xoodyak-384-DOM1-v1/pdi_shared_2.txt" }
G_FNAME_SDI = { file = "KAT/Xoodyak-384-DOM1-v1/sdi_shared_2.txt" }
G_FNAME_DO = { file = "KAT/Xoodyak-384-DOM1-v1/do.txt" }
# G_FNAME_PDI = { file = "BENCH_KAT/Xoodyak-384-DOM1-v1/timing_tests/pdi_shared_2.txt" }
# G_FNAME_SDI = { file = "BENCH_KAT/Xoodyak-384-DOM1-v1/timing_tests/sdi_shared_2.txt" }
# G_FNAME_DO = { file  = "BENCH_KAT/Xoodyak-384-DOM1-v1/timing_tests/do.txt" }
G_TEST_MODE = 4 # 1: stall inputs and outputs
# G_RANDOM_STALL = true
G_TIMEOUT_CYCLES = 1000
G_MAX_FAILURES = 0

[lwc.aead]
algorithm = "xoodyakv1"
# key_bits = 128
# npub_bits = 128
# tag_bits = 128
# input_sequence.encrypt = [ "npub", "ad", "pt", "tag" ]
# input_sequence.decrypt = [ "npub", "ad", "ct", "tag" ]

# [lwc.hash]
# algorithm = "" ###### (hashing is not supported)
# digest_bits = 128

[lwc.ports]
# pdi.bit_width = 32
pdi.num_shares = 2
rdi.bit_width = 384
# sdi.bit_width = 32
sdi.num_shares = 2

[lwc.sca_protection]
target = ["timing", "sda", "dpa"]
order = 1


[flow.vivado_synth]
fpga.part = "xc7a100tftg256-2L"
clock_period = 10