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WbLSdaq_settings.json
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{
name: "RUN", // run settings
outfile: "pulsegen", // file to save data to (appends .h5 automatically)
events: 0, // number of events to grab per channel (0 -> inf)
repeat_times: 0, // number of times to repeat this run (nonzero appends .[number].h5 to outfile)
link_num: 0, // the nth V1718 connected to computer
check_temps_every: 10, // check temps of ADCs every X seconds
arm_last: "master", // index of the digitizer to arm last (generates triggers)
soft_trig: "fast", // index of the digitizer to software trigger before starting acquisition
}
{
name: "LECROY6ZI", // For LeCroy oscilloscopes using VICP remote protocol
index: "scope", // Unique name for this oscilloscope
host: "lescope.dhcp.lbl.gov", // Hostname or IP for the scope
port: 1861, // Port to connect to (1861 for VICP)
timeout: 10.0, // Socket read timeout in seconds
load: 1, // Index [1-6] of the saved state to recall and arm
}
{
name: "V65XX", // V6533 global settings
index: "pos0", // To match card to subtables, data storage
base_address: 0x22220000, // hex address offset for VME
//ch0: {
// enabled: true, // Channel enable
// v_set: 50.0, // Voltage set point
// v_max: 2000.0, // Max voltage
// i_max: 400.0, // Max current
// r_up: 1, // V/s ramp up speed
// r_down: 50, // V/s ramp down speed
// trip: 5.0, // s to tolerate over current
// ramp_off: true, // ramp down (true) or kill down (false)
//},
}
{
name: "V65XX", // V6533 global settings
index: "neg0", // To match card to subtables, data storage
base_address: 0x55550000, // hex address offset for VME
//ch0: {
// enabled: true, // Channel enable
// v_set: -50.0, // Voltage set point
// v_max: -1000.0, // Max voltage
// i_max: 400.0, // Max current
// r_up: 1, // V/s ramp up speed
// r_down: 50, // V/s ramp down speed
// trip: 5.0, // s to tolerate over current
// ramp_off: true, // ramp down (true) or kill down (false)
//},
}
{
name: "V1730", // V1730 global settings
index: "master", // To match card to subtables, data storage
base_address: 0xAAAA0000, // hex address offset for VME
buffer_size: 5, // Readout circular buffer size in MiB
global_majority_level: 0, // global_majority_level+1 requests required for global trigger
external_trigger_enable: false, // trig in fires a global trigger
external_trigger_out: false, // route trig in to trig out
software_trigger_enable: false, // software trigger fires a global trigger
software_trigger_out: false, // route software trigger to trig out
trig_out_logic: 0, // Choose index [OR, AND, MAJORITY] how trigger requests fire trig out
trig_out_majority_level: 0, // trig_out_majority_level+1 requests required for trig out in MAJORITY mode
aggregates_per_transfer: 5, // maximum board aggregates to read out during a single transfer
}
{
name: "GR0", // channel 0 and 1 common settings
index: "master", // master channel specific settings
local_logic: 1, // what to propagate as trigger requests [AND, EVEN, ODD, OR]
valid_logic: 1, // how to validate a local trigger [AND, MOTHER, COUPLE, OR]
request_global_trigger: true, // send global trigger request on local trigger
request_trig_out: true, // send trigger out request on local trigger
validation_mask: [true,false,false,false,false,false,false,false], // how each couple shaped trigger participates in validation
validation_mode: 0, // Choose index [OR, AND, MAJORITY] how to combine enabled shaped triggers
validation_majority_level: 0, // validation_majority_level+1 requests required for validation in MAJORITY mode
record_length: 500, // samples to acquire per trigger
events_per_buffer: 5, // events per readout buffer
}
// duplicate this table for having multiple channels active (change index)
{
name: "CH0", // for channel 0
index: "master", // master channel specific settings
enabled: true, // record events from this channel
dc_offset: 0, // volts to shift the input by (-1V to 1V)
baseline_average: 2, // Choose index [fixed,16,64,256,1024] samples to average baseline
pulse_polarity: 0, // Choose index [POSITIVE, NEGATIVE] direction of pulses to trigger on
trigger_threshold: 100, // counts past baseline to trigger
self_trigger: false, // local trigger triggers local acquisition
pre_trigger: 250, // samples to acquire before the trigger
gate_offset: 10, // samples before the trigger to start gates
short_gate: 50, // short integration window
long_gate: 100, // long integration window
charge_sensitivity: 2, // Choose index [5fC,20fC,80fC,320fC,1280fC] for 2Vpp
shaped_trigger_width: 10, // number of samples to send trigger request after trigger
trigger_holdoff: 100, // inhibit triggers for this many samples after trigger
trigger_type: 0, // Choose index [Normal, Coincidence, RESERVED, Anti-coincidence] how to handle trigger validation
}
{
name: "V1742", // V1742 global settings
index: "fast", // To match card to subtables, data storage
base_address: 0xBBBB0000, // hex address offset for VME
buffer_size: 5, // Readout circular buffer size in MiB
tr_enabled: false, // Trigger on TR0,TR1 over/under threshold
tr_readout: false, // Save TR0,TR1 traces in readout
tr_polarity: 0, // Choose index [POSITIVE,NEGATIVE] direction of pulses to trigger on
tr0_threshold: 0x6666, // TR0 trigger threshold (see docs)
tr0_dc_offset: 0x8000, // TR0 dc offset added to signal (see docs)
tr1_threshold: 0x6666, // TR0 trigger threshold (see docs)
tr1_dc_offset: 0x8000, // TR0 dc offset added to signal (see docs)
num_samples: 0, // Choose index [1024, 520, 256, 136]
sample_freq: 2, // Choose index [5 GHz, 2.5 GHz, 1 GHz]
software_trigger: false, // Global trigger on software trigger
external_trigger: true, // Global trigger on software trigger
software_trigger_out: true, // Trigger out on software trigger
external_trigger_out: false, // Trigger out on software trigger
trigger_offset: 1, // Multiples of 8.5ns to wait after trigger before digitizing samples
events_per_transfer: 10, // Max events to transfer during one VME BLT
}
// duplicate this table for having multiple groups active (change index)
{
name: "GR0",
index: "fast",
enabled: true,
dc_offsets: [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0], //16 bit (-1V, 1V) offset added to signal
}